GCEA

GCEA names the stage where traffic leaves the on-chip cache hierarchy toward DRAM, covering memory-channel interfaces, the system arbiter (SARB), and return paths. Use these panels when analyzing bandwidth limits or memory-controller behavior after GL2.

The sections below list RDNA3.5 (gfx1151) GCEA / DRAM interface metric descriptions.

For on-chip GL2 cache tables, see GL2.

Note

Panel YAMLs label DRAM read/write, SARB, and return-interface metrics together under this memory hierarchy stage.

DRAM read interface

RDNA 3.5 (gfx1151)

Metric	Description	Unit
DRAM Read Requests	Number of read requests sent to system memory. RDNA 3.5 APUs use DDR5/LPDDR5 system memory. High read request counts indicate memory-intensive workloads that may be bandwidth limited.	Count per Normalization Unit
DRAM Read Chained Requests	Number of sequential read request chains to system memory. Chained requests combine multiple sequential accesses for better memory efficiency. High chain counts indicate good memory access patterns.	Count per Normalization Unit
DRAM Read Banks Active	Number of system memory banks with pending read requests. More active banks enable better memory-level parallelism. Low bank utilization may indicate suboptimal access patterns limiting bandwidth.	Count per Normalization Unit
DRAM Read Size (32B increments)	Total volume of read data transferred from system memory. This metric helps quantify memory read bandwidth consumption. Compare with theoretical bandwidth to assess memory utilization.	Count per Normalization Unit

DRAM write interface

RDNA 3.5 (gfx1151)

Metric	Description	Unit
DRAM Write Requests	Number of write requests sent to system memory. High write request counts indicate write-intensive workloads. Combined with read requests, this shows total memory traffic.	Count per Normalization Unit
DRAM Write Chained Requests	Number of sequential write request chains to system memory. Chained writes combine sequential stores for better efficiency. High chain counts indicate good write access patterns.	Count per Normalization Unit
DRAM Write Banks Active	Number of system memory banks with pending write requests. Higher bank utilization enables better write bandwidth. Low values may indicate access pattern issues.	Count per Normalization Unit
DRAM Write Size (32B increments)	Total volume of write data transferred to system memory. This quantifies memory write bandwidth consumption. High values indicate write-intensive workloads.	Count per Normalization Unit

System Arbiter (SARB)

RDNA 3.5 (gfx1151)

Metric	Description	Unit
SARB Busy	Percentage of cycles the System Arbiter is actively processing memory requests. High busy percentage indicates significant off-chip memory traffic. This is a key indicator of memory-bound behavior.	Percent
SARB Stalled	Percentage of cycles the System Arbiter has requests but cannot make progress due to downstream backpressure. High stall rates indicate memory bandwidth saturation or system memory contention.	Percent
SARB Starving	Percentage of cycles the System Arbiter has no requests to process. High starvation indicates compute-bound workloads or effective caching reducing memory traffic.	Percent
SARB Total Requests	Total memory requests processed by the System Arbiter. This represents all traffic between the GPU caches and system memory interface, including reads, writes, and atomics.	Count per Normalization Unit
SARB DRAM Requests	Memory requests specifically destined for system memory (DRAM). This excludes requests serviced by other system components. High counts indicate memory-intensive workloads.	Count per Normalization Unit

Return interface

RDNA 3.5 (gfx1151)

Metric	Description	Unit
Read Returns	Number of completed read operations returning data from system memory. Each return delivers requested data to the GPU caches. High counts indicate successful memory read traffic.	Count per Normalization Unit
Write Returns	Number of completed write acknowledgements from system memory. Each return confirms successful data write. High counts indicate write-intensive workloads completing successfully.	Count per Normalization Unit
Probe Requests	Number of cache coherency probe operations. These occur when external agents or system components require cache synchronization. High counts may indicate coherency traffic impacting performance.	Count per Normalization Unit

Memory chart: GCEA to system memory

The following Memory Chart table aligns with the on-screen flow from GCEA out to system memory.

Memory chart - GCEA to system memory

RDNA 3.5 (gfx1151)

Metric	Description	Unit
SARB Utilization	Percentage of cycles the System Arbiter is actively processing memory requests. The arbiter handles traffic between the GPU caches and system memory interface. High utilization indicates significant off-chip memory activity.	Percent
DRAM Read Bandwidth	Achieved read bandwidth to system memory. RDNA 3.5 APUs use DDR5/LPDDR5 system memory. High read bandwidth indicates memory-intensive read patterns. This is a key metric for identifying memory-bound workloads.	Bytes/s
DRAM Write Bandwidth	Achieved write bandwidth to system memory. High write bandwidth indicates write-intensive workloads. Combined with read bandwidth, this shows total memory traffic between the GPU and system memory.	Bytes/s
SARB Stall Rate	Percent of GCEA sample cycles the System Arbiter (SARB) was stalled. Formula: 100 * GCEA_SARB_STALLED_sum / GCEA_ALWAYS_COUNT_sum.	Percent
DRAM Read Requests	DRAM read requests per client group from the GCEA memory path (GCEA_RDRAM_REQ_PER_CLIGRP_sum / $denom).	Requests per Normalization Unit
DRAM Write Requests	DRAM write requests per client group from the GCEA memory path (GCEA_WDRAM_REQ_PER_CLIGRP_sum / $denom).	Requests per Normalization Unit
Read Returns	Valid read-return events on the GCEA return path per normalization unit (GCEA_RRET_VLD_sum / $denom).	Count per Normalization Unit
Write Returns	Valid write-return events on the GCEA return path per normalization unit (GCEA_WRET_VLD_sum / $denom).	Count per Normalization Unit