GL2

On gfx115x, GL2 Cache (RDNA naming for what Instinct documentation refers to as L2/TCC) is the last-level GFX on-chip cache for most clients before traffic reaches the memory system.

After GL2, traffic proceeds toward DRAM through GCEA and related interfaces; those panels are documented under GCEA.

For Instinct L2 (TCC) coherence, channel hashing, and fabric metrics on CDNA architecture across MI-series GPUs, see L2 cache (TCC) under CDNA-CDNA4.

Note

The GL2 Cache is also referred to as GL2C in some contexts. Hardware counter names (for example, GL2C_HIT_sum) retain the GL2C prefix.

GL2 Cache panels

GL2 Cache performance

RDNA 3.5 (gfx115x)

Metric	Description	Unit
GL2 Cache Hit Rate	Percentage of GL2 cache requests serviced from cache without forwarding through GCEA (Graphics Core Efficiency Arbiter). GL2 cache is the GPU’s final on-chip cache before accessing system memory. Higher hit rates significantly reduce memory bandwidth pressure and improve performance.	Percent
GL2 Cache Hits	Number of GL2 cache requests that were serviced from cache. High hit counts relative to total requests indicate effective caching. Low hit counts suggest memory-bound workloads or poor data locality.	Count per Normalization Unit
GL2 Cache Misses	Number of GL2 cache requests that missed and required fetching through GCEA (Graphics Core Efficiency Arbiter). High miss counts indicate heavy memory traffic. Consider improving data locality or reducing working set size.	Count per Normalization Unit

GL2 Cache request statistics

RDNA 3.5 (gfx115x)

Metric	Description	Unit
Total Requests	Total number of requests received by the GL2 cache from all GL1 caches and other clients. This represents the aggregate memory traffic at the GPU’s final on-chip cache.	Count per Normalization Unit
Read Requests	Number of read requests to the GL2 cache. High read counts indicate memory-intensive load operations. Compare with hit rate to assess GL2 cache effectiveness for reads.	Count per Normalization Unit
Write Requests	Number of write requests to the GL2 cache. Write traffic includes stores and cache writebacks from GL1. High write counts indicate write-intensive workloads.	Count per Normalization Unit
Atomic Requests	Number of atomic memory operations processed by the GL2 cache. Atomics provide thread-safe memory access but may serialize at contended addresses. High counts may impact performance.	Count per Normalization Unit
EA Read Requests (DRAM)	Number of read requests forwarded from GL2 cache through GCEA (Graphics Core Efficiency Arbiter). These requests go toward system memory, though they may be served by system-level caches before reaching DRAM. High counts indicate memory-bound workloads.	Count per Normalization Unit
EA Write Requests (DRAM)	Number of write requests forwarded from GL2 cache through GCEA (Graphics Core Efficiency Arbiter). These include evictions and writebacks going toward system memory. High counts indicate write-intensive workloads consuming memory bandwidth.	Count per Normalization Unit

GL2 Cache bandwidth

RDNA 3.5 (gfx115x)

Metric	Description	Unit
GL2 Cache Read BW	Achieved read bandwidth at the GL2 cache level. This represents total read traffic from GL1 caches to GL2. High bandwidth indicates memory-intensive read patterns.	Bytes/s
GL2 Cache Write BW	Achieved write bandwidth at the GL2 cache level. This represents total write traffic from GL1 caches to GL2. High bandwidth indicates memory-intensive write patterns.	Bytes/s

Memory chart: GL2 cache

The following Memory Chart table aligns with the on-screen flow through GL2.

Memory chart - GL2 cache

RDNA 3.5 (gfx115x)

Metric	Description	Unit
GL2 Cache Hit Rate	Percentage of L2 cache requests that hit in cache. GL2 cache is the GPU’s final on-chip cache before accessing system memory via GCEA. High hit rates reduce memory bandwidth pressure. Low hit rates cause traffic to system memory, increasing latency.	Percent