include/hip/hip_deprecated.h File Reference

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Data Structures | Functions

hip_deprecated.h File Reference

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Data Structures
struct	hipDeviceProp_tR0000

Functions
hipError_t	hipGetDevicePropertiesR0000 (hipDeviceProp_tR0000 *prop, int device)
hipError_t	hipChooseDeviceR0000 (int *device, const hipDeviceProp_tR0000 *prop)

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Data Structure Documentation

◆ hipDeviceProp_tR0000

struct hipDeviceProp_tR0000

Collaboration diagram for hipDeviceProp_tR0000:

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Data Fields
hipDeviceArch_t	arch	Architectural feature flags. New for HIP.
int	asicRevision	Revision of the GPU in this device.
int	canMapHostMemory	Check whether HIP can map host memory.
int	clockInstructionRate	Frequency in khz of the timer used by the device-side "clock*" instructions. New for HIP.
int	clockRate	Max clock frequency of the multiProcessors in khz.
int	computeMode	Compute mode.
int	concurrentKernels	Device can possibly execute multiple kernels concurrently.
int	concurrentManagedAccess	Device can coherently access managed memory concurrently with the CPU
int	cooperativeLaunch	HIP device supports cooperative launch.
int	cooperativeMultiDeviceLaunch	HIP device supports cooperative launch on multiple devices
int	cooperativeMultiDeviceUnmatchedBlockDim	HIP device supports cooperative launch on multiple devices with unmatched block dimensions
int	cooperativeMultiDeviceUnmatchedFunc	HIP device supports cooperative launch on multiple devices with unmatched functions
int	cooperativeMultiDeviceUnmatchedGridDim	HIP device supports cooperative launch on multiple devices with unmatched grid dimensions
int	cooperativeMultiDeviceUnmatchedSharedMem	HIP device supports cooperative launch on multiple devices with unmatched shared memories
int	directManagedMemAccessFromHost	Host can directly access managed memory on the device without migration
int	ECCEnabled	Device has ECC support enabled.
int	gcnArch	DEPRECATED: use gcnArchName instead.
char	gcnArchName[256]	AMD GCN Arch Name.
unsigned int *	hdpMemFlushCntl	Addres of HDP_MEM_COHERENCY_FLUSH_CNTL register.
unsigned int *	hdpRegFlushCntl	Addres of HDP_REG_COHERENCY_FLUSH_CNTL register.
int	integrated	APU vs dGPU.
int	isLargeBar	1: if it is a large PCI bar device, else 0
int	isMultiGpuBoard	1 if device is on a multi-GPU board, 0 if not.
int	kernelExecTimeoutEnabled	Run time limit for kernels executed on the device.
int	l2CacheSize	L2 cache size.
int	major	Major compute capability. On HCC, this is an approximation and features may differ from CUDA CC. See the arch feature flags for portable ways to query feature caps.
int	managedMemory	Device supports allocating managed memory on this system.
int	maxGridSize[3]	Max grid dimensions (XYZ).
size_t	maxSharedMemoryPerMultiProcessor	Maximum Shared Memory Per Multiprocessor.
int	maxTexture1D	Maximum number of elements in 1D images.
int	maxTexture1DLinear	Maximum size for 1D textures bound to linear memory.
int	maxTexture2D[2]	Maximum dimensions (width, height) of 2D images, in image elements.
int	maxTexture3D[3]	Maximum dimensions (width, height, depth) of 3D images, in image elements
int	maxThreadsDim[3]	Max number of threads in each dimension (XYZ) of a block.
int	maxThreadsPerBlock	Max work items per work group or workgroup max size.
int	maxThreadsPerMultiProcessor	Maximum resident threads per multi-processor.
int	memoryBusWidth	Global memory bus width in bits.
int	memoryClockRate	Max global memory clock frequency in khz.
size_t	memPitch	Maximum pitch in bytes allowed by memory copies.
int	minor	Minor compute capability. On HCC, this is an approximation and features may differ from CUDA CC. See the arch feature flags for portable ways to query feature caps.
int	multiProcessorCount	Number of multi-processors. When the GPU works in Compute Unit (CU) mode, this value equals the number of CUs; when in Workgroup Processor (WGP) mode, this value equels half of CUs, because a single WGP contains two CUs.
char	name[256]	Device name.
int	pageableMemoryAccess	Device supports coherently accessing pageable memory without calling hipHostRegister on it
int	pageableMemoryAccessUsesHostPageTables	Device accesses pageable memory via the host's page tables
int	pciBusID	PCI Bus ID.
int	pciDeviceID	PCI Device ID.
int	pciDomainID	PCI Domain ID.
int	regsPerBlock	Registers per block.
size_t	sharedMemPerBlock	Size of shared memory region (in bytes).
int	tccDriver	1:If device is Tesla device using TCC driver, else 0
size_t	textureAlignment	Alignment requirement for textures.
size_t	texturePitchAlignment	Pitch alignment requirement for texture references bound to pitched memory
size_t	totalConstMem	Size of shared memory region (in bytes).
size_t	totalGlobalMem	Size of global memory region (in bytes).
int	warpSize	Warp size.

Function Documentation

◆ hipChooseDeviceR0000()

hipError_t hipChooseDeviceR0000	(	int *	device,
		const hipDeviceProp_tR0000 *	prop
	)

◆ hipGetDevicePropertiesR0000()

hipError_t hipGetDevicePropertiesR0000	(	hipDeviceProp_tR0000 *	prop,
		int	device
	)