amdsmi.h Source File

amdsmi.h Source File#

AMD SMI: amdsmi.h Source File
 /*
  * =============================================================================
  * The University of Illinois/NCSA
  * Open Source License (NCSA)
  *
  * Copyright (c) 2023, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Developed by:
  *
  *                 AMD Research and AMD ROC Software Development
  *
  *                 Advanced Micro Devices, Inc.
  *
  *                 www.amd.com
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to
  * deal with the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  *  - Redistributions of source code must retain the above copyright notice,
  *    this list of conditions and the following disclaimers.
  *  - Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimers in
  *    the documentation and/or other materials provided with the distribution.
  *  - Neither the names of <Name of Development Group, Name of Institution>,
  *    nor the names of its contributors may be used to endorse or promote
  *    products derived from this Software without specific prior written
  *    permission.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS WITH THE SOFTWARE.
  *
  */
 #ifndef INCLUDE_AMDSMI_H_
 #define INCLUDE_AMDSMI_H_
  
 #include <stdlib.h>
 #include <stdbool.h>
 #ifdef __cplusplus
 extern "C" {
 #include <cstdint>
 #ifdef ENABLE_ESMI_LIB
     #include <e_smi/e_smi.h>
 #endif
  
 #else
 #include <stdint.h>
 #endif  // __cplusplus
  
 typedef enum {
   AMDSMI_INIT_ALL_PROCESSORS = 0xFFFFFFFF,  
   AMDSMI_INIT_AMD_CPUS = (1 << 0),
   AMDSMI_INIT_AMD_GPUS = (1 << 1),
   AMDSMI_INIT_NON_AMD_CPUS = (1 << 2),
   AMDSMI_INIT_NON_AMD_GPUS = (1 << 3),
   AMDSMI_INIT_AMD_APUS = (AMDSMI_INIT_AMD_CPUS | AMDSMI_INIT_AMD_GPUS) // Default option
 } amdsmi_init_flags_t;
  
 /* Maximum size definitions AMDSMI */
 #define AMDSMI_MAX_MM_IP_COUNT        8
 #define AMDSMI_MAX_DATE_LENGTH        32 
 #define AMDSMI_MAX_STRING_LENGTH      64
 #define AMDSMI_NORMAL_STRING_LENGTH   32
 #define AMDSMI_MAX_DEVICES            32
 #define AMDSMI_MAX_NAME               32
 #define AMDSMI_MAX_DRIVER_VERSION_LENGTH 80
 #define AMDSMI_PRODUCT_NAME_LENGTH 128
 #define AMDSMI_MAX_CONTAINER_TYPE    2
 #define AMDSMI_MAX_CACHE_TYPES 10
 #define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK 64
  
 #define AMDSMI_GPU_UUID_SIZE 38
  
 #define CENTRIGRADE_TO_MILLI_CENTIGRADE 1000
  
 #define AMDSMI_NUM_HBM_INSTANCES 4
  
 #define AMDSMI_MAX_NUM_VCN 4
  
 #define AMDSMI_MAX_NUM_CLKS 4
  
 #define AMDSMI_MAX_NUM_XGMI_LINKS 8
  
 #define AMDSMI_MAX_NUM_GFX_CLKS 8
  
 #define AMDSMI_MAX_AID 4
  
 #define AMDSMI_MAX_ENGINES 8
  
 #define AMDSMI_MAX_NUM_JPEG 32
  
 /* string format */
 #define AMDSMI_TIME_FORMAT "%02d:%02d:%02d.%03d"
 #define AMDSMI_DATE_FORMAT "%04d-%02d-%02d:%02d:%02d:%02d.%03d"
  
 #define AMDSMI_LIB_VERSION_YEAR 24
  
 #define AMDSMI_LIB_VERSION_MAJOR 5
  
 #define AMDSMI_LIB_VERSION_MINOR 2
  
 #define AMDSMI_LIB_VERSION_RELEASE 0
  
 #define AMDSMI_LIB_VERSION_CREATE_STRING(YEAR, MAJOR, MINOR, RELEASE) (#YEAR "." #MAJOR "." #MINOR "." #RELEASE)
 #define AMDSMI_LIB_VERSION_EXPAND_PARTS(YEAR_STR, MAJOR_STR, MINOR_STR, RELEASE_STR) AMDSMI_LIB_VERSION_CREATE_STRING(YEAR_STR, MAJOR_STR, MINOR_STR, RELEASE_STR)
 #define AMDSMI_LIB_VERSION_STRING AMDSMI_LIB_VERSION_EXPAND_PARTS(AMDSMI_LIB_VERSION_YEAR, AMDSMI_LIB_VERSION_MAJOR, AMDSMI_LIB_VERSION_MINOR, AMDSMI_LIB_VERSION_RELEASE)
  
 typedef enum {
   AMDSMI_MM_UVD,
   AMDSMI_MM_VCE,
   AMDSMI_MM_VCN,
   AMDSMI_MM__MAX
 } amdsmi_mm_ip_t;
  
 typedef enum {
   CONTAINER_LXC,
   CONTAINER_DOCKER,
 } amdsmi_container_types_t;
  
 typedef void *amdsmi_processor_handle;
 typedef void *amdsmi_socket_handle;
 #ifdef ENABLE_ESMI_LIB
 typedef void *amdsmi_cpusocket_handle;
 #endif
  
 typedef enum {
   UNKNOWN = 0,
   AMD_GPU,
   AMD_CPU,
   NON_AMD_GPU,
   NON_AMD_CPU,
   AMD_CPU_CORE,
   AMD_APU
 } processor_type_t;
  
 // Please avoid status codes that are multiples of 256 (256, 512, etc..)
 // Return values in the shell get modulo 256 applied, meaning any multiple of 256 ends up as 0
 typedef enum {
     AMDSMI_STATUS_SUCCESS = 0,  
     // Library usage errors
     AMDSMI_STATUS_INVAL = 1,  
     AMDSMI_STATUS_NOT_SUPPORTED = 2,  
     AMDSMI_STATUS_NOT_YET_IMPLEMENTED = 3,  
     AMDSMI_STATUS_FAIL_LOAD_MODULE = 4,  
     AMDSMI_STATUS_FAIL_LOAD_SYMBOL = 5,  
     AMDSMI_STATUS_DRM_ERROR = 6,  
     AMDSMI_STATUS_API_FAILED = 7,  
     AMDSMI_STATUS_TIMEOUT = 8,  
     AMDSMI_STATUS_RETRY = 9,  
     AMDSMI_STATUS_NO_PERM = 10,  
     AMDSMI_STATUS_INTERRUPT = 11,  
     AMDSMI_STATUS_IO = 12,  
     AMDSMI_STATUS_ADDRESS_FAULT = 13,  
     AMDSMI_STATUS_FILE_ERROR = 14,  
     AMDSMI_STATUS_OUT_OF_RESOURCES = 15,  
     AMDSMI_STATUS_INTERNAL_EXCEPTION = 16,  
     AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS = 17,  
     AMDSMI_STATUS_INIT_ERROR = 18,  
     AMDSMI_STATUS_REFCOUNT_OVERFLOW = 19,  
     // Device related errors
     AMDSMI_STATUS_BUSY = 30,  
     AMDSMI_STATUS_NOT_FOUND = 31,  
     AMDSMI_STATUS_NOT_INIT = 32,  
     AMDSMI_STATUS_NO_SLOT = 33,  
     AMDSMI_STATUS_DRIVER_NOT_LOADED = 34,  
     // Data and size errors
     AMDSMI_STATUS_NO_DATA = 40,  
     AMDSMI_STATUS_INSUFFICIENT_SIZE = 41,  
     AMDSMI_STATUS_UNEXPECTED_SIZE = 42,  
     AMDSMI_STATUS_UNEXPECTED_DATA = 43,  
     //esmi errors
     AMDSMI_STATUS_NON_AMD_CPU = 44, 
     AMDSMI_NO_ENERGY_DRV = 45, 
     AMDSMI_NO_MSR_DRV = 46, 
     AMDSMI_NO_HSMP_DRV = 47, 
     AMDSMI_NO_HSMP_SUP = 48, 
     AMDSMI_NO_HSMP_MSG_SUP = 49, 
     AMDSMI_HSMP_TIMEOUT = 50,  
     AMDSMI_NO_DRV = 51,  
     AMDSMI_FILE_NOT_FOUND = 52, 
     AMDSMI_ARG_PTR_NULL = 53,   
     AMDSMI_STATUS_AMDGPU_RESTART_ERR = 54, 
     AMDSMI_STATUS_SETTING_UNAVAILABLE = 55, 
  
     // General errors
     AMDSMI_STATUS_MAP_ERROR = 0xFFFFFFFE,  
     AMDSMI_STATUS_UNKNOWN_ERROR = 0xFFFFFFFF,  
 } amdsmi_status_t;
  
 typedef enum {
     CLK_TYPE_SYS = 0x0,   
     CLK_TYPE_FIRST = CLK_TYPE_SYS,
     CLK_TYPE_GFX = CLK_TYPE_SYS,
     CLK_TYPE_DF,  
     CLK_TYPE_DCEF,   
     CLK_TYPE_SOC,
     CLK_TYPE_MEM,
     CLK_TYPE_PCIE,
     CLK_TYPE_VCLK0,
     CLK_TYPE_VCLK1,
     CLK_TYPE_DCLK0,
     CLK_TYPE_DCLK1,
     CLK_TYPE__MAX = CLK_TYPE_DCLK1
 } amdsmi_clk_type_t;
  
 typedef enum {
   COMPUTE_PARTITION_INVALID = 0,
   COMPUTE_PARTITION_CPX, 
   COMPUTE_PARTITION_SPX, 
   COMPUTE_PARTITION_DPX, 
   COMPUTE_PARTITION_TPX, 
   COMPUTE_PARTITION_QPX  
 } amdsmi_compute_partition_type_t;
  
 typedef enum {
   MEMORY_PARTITION_UNKNOWN = 0,
   MEMORY_PARTITION_NPS1,  
   MEMORY_PARTITION_NPS2,  
   MEMORY_PARTITION_NPS4,  
   MEMORY_PARTITION_NPS8,  
 } amdsmi_memory_partition_type_t;
  
 typedef enum {
     TEMPERATURE_TYPE_EDGE,
     TEMPERATURE_TYPE_FIRST = TEMPERATURE_TYPE_EDGE,
     TEMPERATURE_TYPE_HOTSPOT,
     TEMPERATURE_TYPE_JUNCTION = TEMPERATURE_TYPE_HOTSPOT,
     TEMPERATURE_TYPE_VRAM,
     TEMPERATURE_TYPE_HBM_0,
     TEMPERATURE_TYPE_HBM_1,
     TEMPERATURE_TYPE_HBM_2,
     TEMPERATURE_TYPE_HBM_3,
     TEMPERATURE_TYPE_PLX,
     TEMPERATURE_TYPE__MAX = TEMPERATURE_TYPE_PLX
 } amdsmi_temperature_type_t;
  
 typedef enum {
     FW_ID_SMU = 1,
     FW_ID_FIRST = FW_ID_SMU,
     FW_ID_CP_CE,
     FW_ID_CP_PFP,
     FW_ID_CP_ME,
     FW_ID_CP_MEC_JT1,
     FW_ID_CP_MEC_JT2,
     FW_ID_CP_MEC1,
     FW_ID_CP_MEC2,
     FW_ID_RLC,
     FW_ID_SDMA0,
     FW_ID_SDMA1,
     FW_ID_SDMA2,
     FW_ID_SDMA3,
     FW_ID_SDMA4,
     FW_ID_SDMA5,
     FW_ID_SDMA6,
     FW_ID_SDMA7,
     FW_ID_VCN,
     FW_ID_UVD,
     FW_ID_VCE,
     FW_ID_ISP,
     FW_ID_DMCU_ERAM, /*eRAM*/
     FW_ID_DMCU_ISR,  /*ISR*/
     FW_ID_RLC_RESTORE_LIST_GPM_MEM,
     FW_ID_RLC_RESTORE_LIST_SRM_MEM,
     FW_ID_RLC_RESTORE_LIST_CNTL,
     FW_ID_RLC_V,
     FW_ID_MMSCH,
     FW_ID_PSP_SYSDRV,
     FW_ID_PSP_SOSDRV,
     FW_ID_PSP_TOC,
     FW_ID_PSP_KEYDB,
     FW_ID_DFC,
     FW_ID_PSP_SPL,
     FW_ID_DRV_CAP,
     FW_ID_MC,
     FW_ID_PSP_BL,
     FW_ID_CP_PM4,
     FW_ID_RLC_P,
     FW_ID_SEC_POLICY_STAGE2,
     FW_ID_REG_ACCESS_WHITELIST,
     FW_ID_IMU_DRAM,
     FW_ID_IMU_IRAM,
     FW_ID_SDMA_TH0,
     FW_ID_SDMA_TH1,
     FW_ID_CP_MES,
     FW_ID_MES_KIQ,
     FW_ID_MES_STACK,
     FW_ID_MES_THREAD1,
     FW_ID_MES_THREAD1_STACK,
     FW_ID_RLX6,
     FW_ID_RLX6_DRAM_BOOT,
     FW_ID_RS64_ME,
     FW_ID_RS64_ME_P0_DATA,
     FW_ID_RS64_ME_P1_DATA,
     FW_ID_RS64_PFP,
     FW_ID_RS64_PFP_P0_DATA,
     FW_ID_RS64_PFP_P1_DATA,
     FW_ID_RS64_MEC,
     FW_ID_RS64_MEC_P0_DATA,
     FW_ID_RS64_MEC_P1_DATA,
     FW_ID_RS64_MEC_P2_DATA,
     FW_ID_RS64_MEC_P3_DATA,
     FW_ID_PPTABLE,
     FW_ID_PSP_SOC,
     FW_ID_PSP_DBG,
     FW_ID_PSP_INTF,
     FW_ID_RLX6_CORE1,
     FW_ID_RLX6_DRAM_BOOT_CORE1,
     FW_ID_RLCV_LX7,
     FW_ID_RLC_SAVE_RESTORE_LIST,
     FW_ID_ASD,
     FW_ID_TA_RAS,
     FW_ID_TA_XGMI,
     FW_ID_RLC_SRLG,
     FW_ID_RLC_SRLS,
     FW_ID_PM,
     FW_ID_DMCU,
     FW_ID__MAX
 } amdsmi_fw_block_t;
  
  
 typedef enum {
   VRAM_TYPE_UNKNOWN = 0,
   VRAM_TYPE_GDDR1 = 1,
   VRAM_TYPE_DDR2 = 2,
   VRAM_TYPE_GDDR3 = 3,
   VRAM_TYPE_GDDR4 = 4,
   VRAM_TYPE_GDDR5 = 5,
   VRAM_TYPE_HBM = 6,
   VRAM_TYPE_DDR3 = 7,
   VRAM_TYPE_DDR4 = 8,
   VRAM_TYPE_GDDR6 = 9,
   VRAM_TYPE__MAX = VRAM_TYPE_GDDR6
 } amdsmi_vram_type_t;
  
 typedef enum {
     AMDSMI_VRAM_VENDOR__PLACEHOLDER0,
     AMDSMI_VRAM_VENDOR__SAMSUNG,
     AMDSMI_VRAM_VENDOR__INFINEON,
     AMDSMI_VRAM_VENDOR__ELPIDA,
     AMDSMI_VRAM_VENDOR__ETRON,
     AMDSMI_VRAM_VENDOR__NANYA,
     AMDSMI_VRAM_VENDOR__HYNIX,
     AMDSMI_VRAM_VENDOR__MOSEL,
     AMDSMI_VRAM_VENDOR__WINBOND,
     AMDSMI_VRAM_VENDOR__ESMT,
     AMDSMI_VRAM_VENDOR__PLACEHOLDER1,
     AMDSMI_VRAM_VENDOR__PLACEHOLDER2,
     AMDSMI_VRAM_VENDOR__PLACEHOLDER3,
     AMDSMI_VRAM_VENDOR__PLACEHOLDER4,
     AMDSMI_VRAM_VENDOR__PLACEHOLDER5,
     AMDSMI_VRAM_VENDOR__MICRON,
 } amdsmi_vram_vendor_type_t;
  
 typedef struct {
     uint64_t lower_bound;      
     uint64_t upper_bound;      
     uint64_t reserved[2];
 } amdsmi_range_t;
  
 typedef struct {
   uint8_t xgmi_lanes;
   uint64_t xgmi_hive_id;
   uint64_t xgmi_node_id;
   uint32_t index;
   uint32_t reserved[9];
 } amdsmi_xgmi_info_t;
  
 typedef struct {
   uint32_t vram_total;
   uint32_t vram_used;
   uint32_t reserved[2];
 } amdsmi_vram_usage_t;
  
 typedef struct {
   amdsmi_range_t supported_freq_range;
   amdsmi_range_t current_freq_range;
   uint32_t reserved[8];
 } amdsmi_frequency_range_t;
  
 typedef union {
   struct fields_ {
     uint64_t function_number : 3;
     uint64_t device_number : 5;
     uint64_t bus_number : 8;
     uint64_t domain_number : 48;
   } fields;
   uint64_t as_uint;
 } amdsmi_bdf_t;
  
 typedef enum {
   AMDSMI_CARD_FORM_FACTOR_PCIE,
   AMDSMI_CARD_FORM_FACTOR_OAM,
   AMDSMI_CARD_FORM_FACTOR_CEM,
   AMDSMI_CARD_FORM_FACTOR_UNKNOWN
 } amdsmi_card_form_factor_t;
  
 typedef struct {
   struct pcie_static_ {
     uint16_t max_pcie_width;              
     uint32_t max_pcie_speed;              
     uint32_t pcie_interface_version;      
     amdsmi_card_form_factor_t slot_type;  
     uint64_t reserved[10];
   } pcie_static;
   struct pcie_metric_ {
     uint16_t pcie_width;                  
     uint32_t pcie_speed;                  
     uint32_t pcie_bandwidth;              
     uint64_t pcie_replay_count;           
     uint64_t pcie_l0_to_recovery_count;   
     uint64_t pcie_replay_roll_over_count; 
     uint64_t pcie_nak_sent_count;         
     uint64_t pcie_nak_received_count;     
     uint64_t reserved[13];
   } pcie_metric;
   uint64_t reserved[32];
 } amdsmi_pcie_info_t;
  
 typedef struct {
   uint64_t power_cap;           
   uint64_t default_power_cap;   
   uint64_t dpm_cap;             
   uint64_t min_power_cap;       
   uint64_t max_power_cap;       
   uint64_t reserved[3];
 } amdsmi_power_cap_info_t;
  
 typedef struct {
   char    name[AMDSMI_MAX_STRING_LENGTH];
   char    build_date[AMDSMI_MAX_DATE_LENGTH];
   char    part_number[AMDSMI_MAX_STRING_LENGTH];
   char    version[AMDSMI_NORMAL_STRING_LENGTH];
   uint32_t reserved[16];
 } amdsmi_vbios_info_t;
  
 typedef enum {
   AMDSMI_CACHE_PROPERTY_ENABLED = 0x00000001,
   AMDSMI_CACHE_PROPERTY_DATA_CACHE = 0x00000002,
   AMDSMI_CACHE_PROPERTY_INST_CACHE = 0x00000004,
   AMDSMI_CACHE_PROPERTY_CPU_CACHE = 0x00000008,
   AMDSMI_CACHE_PROPERTY_SIMD_CACHE = 0x00000010,
 } amdsmi_cache_property_type_t;
  
 typedef struct {
   uint32_t num_cache_types;
   struct cache_ {
     uint32_t cache_properties;  // amdsmi_cache_property_type_t which is a bitmask
     uint32_t cache_size; /* In KB */
     uint32_t cache_level;
     uint32_t max_num_cu_shared;  /* Indicates how many Compute Units share this cache instance */
     uint32_t num_cache_instance;  /* total number of instance of this cache type */
     uint32_t reserved[3];
   } cache[AMDSMI_MAX_CACHE_TYPES];
   uint32_t reserved[15];
 } amdsmi_gpu_cache_info_t;
  
 typedef struct {
   uint8_t num_fw_info;
   struct fw_info_list_ {
     amdsmi_fw_block_t fw_id;
     uint64_t fw_version;
     uint64_t reserved[2];
   } fw_info_list[FW_ID__MAX];
   uint32_t reserved[7];
 } amdsmi_fw_info_t;
  
 typedef struct {
   char  market_name[AMDSMI_MAX_STRING_LENGTH];
   uint32_t vendor_id;   //< Use 32 bit to be compatible with other platform.
   char vendor_name[AMDSMI_MAX_STRING_LENGTH];
   uint32_t subvendor_id;   //< The subsystem vendor id
   uint64_t device_id;   //< The device id of a GPU
   uint32_t rev_id;
   char asic_serial[AMDSMI_NORMAL_STRING_LENGTH];
   uint16_t oam_id;   //< 0xFFFF if not supported
   uint16_t reserved[37];
 } amdsmi_asic_info_t;
  
 typedef enum {
   AMDSMI_LINK_TYPE_PCIE,
   AMDSMI_LINK_TYPE_XGMI,
   AMDSMI_LINK_TYPE_NOT_APPLICABLE,
   AMDSMI_LINK_TYPE_UNKNOWN
 } amdsmi_link_type_t;
  
 typedef struct {
   uint32_t num_links;   
   struct _links {
     amdsmi_bdf_t bdf;
     uint32_t bit_rate;  
     uint32_t max_bandwidth;   
     amdsmi_link_type_t link_type;   
     uint64_t read;  
     uint64_t write;   
     uint64_t reserved[2];
   } links[AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK];
   uint64_t reserved[7];
 } amdsmi_link_metrics_t;
  
 typedef struct {
   amdsmi_vram_type_t vram_type;
   amdsmi_vram_vendor_type_t vram_vendor;
   uint64_t vram_size_mb;
 } amdsmi_vram_info_t;
  
  
 typedef struct {
   char  driver_version[AMDSMI_MAX_STRING_LENGTH];
   char  driver_date[AMDSMI_MAX_STRING_LENGTH];
   char  driver_name[AMDSMI_MAX_STRING_LENGTH];
 } amdsmi_driver_info_t;
  
 typedef struct {
   char  model_number[AMDSMI_NORMAL_STRING_LENGTH];
   char  product_serial[AMDSMI_NORMAL_STRING_LENGTH];
   char  fru_id[AMDSMI_NORMAL_STRING_LENGTH];
   char  product_name[AMDSMI_PRODUCT_NAME_LENGTH];
   char  manufacturer_name[AMDSMI_NORMAL_STRING_LENGTH];
   uint32_t reserved[32];
 } amdsmi_board_info_t;
  
 typedef struct {
   uint32_t current_socket_power;
   uint32_t average_socket_power;
   uint32_t gfx_voltage;   // GFX voltage measurement in mV
   uint32_t soc_voltage;  // SOC voltage measurement in mV
   uint32_t mem_voltage;  // MEM voltage measurement in mV
   uint32_t power_limit;  // The power limit;
   uint32_t reserved[11];
 } amdsmi_power_info_t;
  
 typedef struct {
   uint32_t cur_clk;
   uint32_t min_clk;
   uint32_t max_clk;
   uint32_t sleep_clk;
   uint32_t reserved[4];
 } amdsmi_clk_info_t;
  
 typedef struct {
   uint32_t gfx_activity;
   uint32_t umc_activity;
   uint32_t mm_activity;
   uint32_t reserved[13];
 } amdsmi_engine_usage_t;
 typedef uint32_t amdsmi_process_handle_t;
  
  
 typedef struct {
   char name[AMDSMI_NORMAL_STRING_LENGTH];
   amdsmi_process_handle_t pid;
   uint64_t mem; 
   struct engine_usage_ {
     uint64_t gfx;
     uint64_t enc;
     uint32_t reserved[12];
   } engine_usage; 
   struct memory_usage_ {
     uint64_t gtt_mem;
     uint64_t cpu_mem;
     uint64_t vram_mem;
     uint32_t reserved[10];
   } memory_usage; 
   char container_name[AMDSMI_NORMAL_STRING_LENGTH];
   uint32_t reserved[4];
 } amdsmi_proc_info_t;
  
  
 #define AMDSMI_MAX_NUM_FREQUENCIES 33
  
 #define AMDSMI_MAX_FAN_SPEED 255
  
 #define AMDSMI_NUM_VOLTAGE_CURVE_POINTS 3
 typedef enum {
   AMDSMI_DEV_PERF_LEVEL_AUTO = 0,       
   AMDSMI_DEV_PERF_LEVEL_FIRST = AMDSMI_DEV_PERF_LEVEL_AUTO,
  
   AMDSMI_DEV_PERF_LEVEL_LOW,              
   AMDSMI_DEV_PERF_LEVEL_HIGH,             
   AMDSMI_DEV_PERF_LEVEL_MANUAL,           
   AMDSMI_DEV_PERF_LEVEL_STABLE_STD,       
   AMDSMI_DEV_PERF_LEVEL_STABLE_PEAK,      
   AMDSMI_DEV_PERF_LEVEL_STABLE_MIN_MCLK,  
   AMDSMI_DEV_PERF_LEVEL_STABLE_MIN_SCLK,  
   AMDSMI_DEV_PERF_LEVEL_DETERMINISM,      
  
   AMDSMI_DEV_PERF_LEVEL_LAST = AMDSMI_DEV_PERF_LEVEL_DETERMINISM,
  
   AMDSMI_DEV_PERF_LEVEL_UNKNOWN = 0x100   
 } amdsmi_dev_perf_level_t;
  
 typedef uintptr_t amdsmi_event_handle_t;
  
 typedef enum {
   AMDSMI_EVNT_GRP_XGMI = 0,         
   AMDSMI_EVNT_GRP_XGMI_DATA_OUT = 10,  
   AMDSMI_EVNT_GRP_INVALID = 0xFFFFFFFF
 } amdsmi_event_group_t;
  
 typedef enum {
   AMDSMI_EVNT_FIRST = AMDSMI_EVNT_GRP_XGMI,
  
   AMDSMI_EVNT_XGMI_FIRST = AMDSMI_EVNT_GRP_XGMI,
   AMDSMI_EVNT_XGMI_0_NOP_TX = AMDSMI_EVNT_XGMI_FIRST,  
   AMDSMI_EVNT_XGMI_0_REQUEST_TX,                    
   AMDSMI_EVNT_XGMI_0_RESPONSE_TX,                   
  
   // ie, Throughput = BEATS/time_running 10^9  bytes/sec
   AMDSMI_EVNT_XGMI_0_BEATS_TX,
   AMDSMI_EVNT_XGMI_1_NOP_TX,                        
   AMDSMI_EVNT_XGMI_1_REQUEST_TX,                        
   AMDSMI_EVNT_XGMI_1_RESPONSE_TX,                   
   AMDSMI_EVNT_XGMI_1_BEATS_TX,                      
  
   AMDSMI_EVNT_XGMI_LAST = AMDSMI_EVNT_XGMI_1_BEATS_TX,   // 5
  
   AMDSMI_EVNT_XGMI_DATA_OUT_FIRST = AMDSMI_EVNT_GRP_XGMI_DATA_OUT,  // 10
  
   /*
    * @brief Events in the AMDSMI_EVNT_GRP_XGMI_DATA_OUT group measure
    * the number of beats sent on an XGMI link. Each beat represents
    * 32 bytes. AMDSMI_EVNT_XGMI_DATA_OUT_n represents the number of
    * outbound beats (each representing 32 bytes) on link n.<br><br>
    *
    * XGMI throughput can be calculated by multiplying a event
    * such as ::AMDSMI_EVNT_XGMI_DATA_OUT_n by 32 and dividing by
    * the time for which event collection occurred,
    * ::amdsmi_counter_value_t.time_running (which is in nanoseconds). To get
    * bytes per second, multiply this value by 10<sup>9</sup>.<br>
    * <br>
    * Throughput = BEATS/time_running * 10<sup>9</sup>  (bytes/second)<br>
    */
   // ie, Throughput = BEATS/time_running 10^9  bytes/sec
   AMDSMI_EVNT_XGMI_DATA_OUT_0 = AMDSMI_EVNT_XGMI_DATA_OUT_FIRST,
   AMDSMI_EVNT_XGMI_DATA_OUT_1,   
   AMDSMI_EVNT_XGMI_DATA_OUT_2,   
   AMDSMI_EVNT_XGMI_DATA_OUT_3,   
   AMDSMI_EVNT_XGMI_DATA_OUT_4,   
   AMDSMI_EVNT_XGMI_DATA_OUT_5,   
   AMDSMI_EVNT_XGMI_DATA_OUT_LAST = AMDSMI_EVNT_XGMI_DATA_OUT_5,
  
   AMDSMI_EVNT_LAST = AMDSMI_EVNT_XGMI_DATA_OUT_LAST,
 } amdsmi_event_type_t;
  
 typedef enum {
   AMDSMI_CNTR_CMD_START = 0,  
   AMDSMI_CNTR_CMD_STOP,       
 } amdsmi_counter_command_t;
  
 typedef struct {
   uint64_t value;            
   uint64_t time_enabled;     
   uint64_t time_running;     
 } amdsmi_counter_value_t;
  
 typedef enum {
   AMDSMI_EVT_NOTIF_VMFAULT = 1,  
   AMDSMI_EVT_NOTIF_FIRST = AMDSMI_EVT_NOTIF_VMFAULT,
   AMDSMI_EVT_NOTIF_THERMAL_THROTTLE = 2,
   AMDSMI_EVT_NOTIF_GPU_PRE_RESET = 3,
   AMDSMI_EVT_NOTIF_GPU_POST_RESET = 4,
  
   AMDSMI_EVT_NOTIF_LAST = AMDSMI_EVT_NOTIF_GPU_POST_RESET
 } amdsmi_evt_notification_type_t;
  
 #define AMDSMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
  
 #define MAX_EVENT_NOTIFICATION_MSG_SIZE 64
  
 typedef struct {
     amdsmi_processor_handle processor_handle;        
     amdsmi_evt_notification_type_t event;     
     char message[MAX_EVENT_NOTIFICATION_MSG_SIZE];  
 } amdsmi_evt_notification_data_t;
  
 typedef enum {
   AMDSMI_TEMP_CURRENT = 0x0,   
   AMDSMI_TEMP_FIRST = AMDSMI_TEMP_CURRENT,
  
   AMDSMI_TEMP_MAX,             
   AMDSMI_TEMP_MIN,             
   AMDSMI_TEMP_MAX_HYST,        
   AMDSMI_TEMP_MIN_HYST,        
   AMDSMI_TEMP_CRITICAL,        
   AMDSMI_TEMP_CRITICAL_HYST,   
   AMDSMI_TEMP_EMERGENCY,       
   AMDSMI_TEMP_EMERGENCY_HYST,  
   AMDSMI_TEMP_CRIT_MIN,        
   AMDSMI_TEMP_CRIT_MIN_HYST,   
   AMDSMI_TEMP_OFFSET,          
   AMDSMI_TEMP_LOWEST,          
   AMDSMI_TEMP_HIGHEST,         
  
   AMDSMI_TEMP_LAST = AMDSMI_TEMP_HIGHEST
 } amdsmi_temperature_metric_t;
  
 typedef enum {
   AMDSMI_VOLT_CURRENT = 0x0,               
  
   AMDSMI_VOLT_FIRST = AMDSMI_VOLT_CURRENT,
   AMDSMI_VOLT_MAX,                         
   AMDSMI_VOLT_MIN_CRIT,                    
   AMDSMI_VOLT_MIN,                         
   AMDSMI_VOLT_MAX_CRIT,                    
   AMDSMI_VOLT_AVERAGE,                     
   AMDSMI_VOLT_LOWEST,                      
   AMDSMI_VOLT_HIGHEST,                     
  
   AMDSMI_VOLT_LAST = AMDSMI_VOLT_HIGHEST
 } amdsmi_voltage_metric_t;
  
 typedef enum {
   AMDSMI_VOLT_TYPE_FIRST = 0,
  
   AMDSMI_VOLT_TYPE_VDDGFX = AMDSMI_VOLT_TYPE_FIRST,  
   AMDSMI_VOLT_TYPE_LAST = AMDSMI_VOLT_TYPE_VDDGFX,
   AMDSMI_VOLT_TYPE_INVALID = 0xFFFFFFFF            
 } amdsmi_voltage_type_t;
  
 typedef enum {
   AMDSMI_PWR_PROF_PRST_CUSTOM_MASK = 0x1,        
   AMDSMI_PWR_PROF_PRST_VIDEO_MASK = 0x2,         
   AMDSMI_PWR_PROF_PRST_POWER_SAVING_MASK = 0x4,  
   AMDSMI_PWR_PROF_PRST_COMPUTE_MASK = 0x8,       
   AMDSMI_PWR_PROF_PRST_VR_MASK = 0x10,           
  
   AMDSMI_PWR_PROF_PRST_3D_FULL_SCR_MASK = 0x20,
   AMDSMI_PWR_PROF_PRST_BOOTUP_DEFAULT = 0x40,    
   AMDSMI_PWR_PROF_PRST_LAST = AMDSMI_PWR_PROF_PRST_BOOTUP_DEFAULT,
  
   AMDSMI_PWR_PROF_PRST_INVALID = 0xFFFFFFFFFFFFFFFF
 } amdsmi_power_profile_preset_masks_t;
  
 typedef enum {
   AMDSMI_GPU_BLOCK_INVALID =   0x0000000000000000,  
   AMDSMI_GPU_BLOCK_FIRST =     0x0000000000000001,
  
   AMDSMI_GPU_BLOCK_UMC = AMDSMI_GPU_BLOCK_FIRST,    
   AMDSMI_GPU_BLOCK_SDMA =      0x0000000000000002,  
   AMDSMI_GPU_BLOCK_GFX =       0x0000000000000004,  
   AMDSMI_GPU_BLOCK_MMHUB =     0x0000000000000008,  
   AMDSMI_GPU_BLOCK_ATHUB =     0x0000000000000010,  
   AMDSMI_GPU_BLOCK_PCIE_BIF =  0x0000000000000020,  
   AMDSMI_GPU_BLOCK_HDP =       0x0000000000000040,  
   AMDSMI_GPU_BLOCK_XGMI_WAFL = 0x0000000000000080,  
   AMDSMI_GPU_BLOCK_DF =        0x0000000000000100,  
   AMDSMI_GPU_BLOCK_SMN =       0x0000000000000200,  
   AMDSMI_GPU_BLOCK_SEM =       0x0000000000000400,  
   AMDSMI_GPU_BLOCK_MP0 =       0x0000000000000800,  
   AMDSMI_GPU_BLOCK_MP1 =       0x0000000000001000,  
   AMDSMI_GPU_BLOCK_FUSE =      0x0000000000002000,  
   AMDSMI_GPU_BLOCK_MCA =       0x0000000000004000,  
   AMDSMI_GPU_BLOCK_VCN =       0x0000000000008000,  
   AMDSMI_GPU_BLOCK_JPEG =      0x0000000000010000,  
   AMDSMI_GPU_BLOCK_IH =        0x0000000000020000,  
   AMDSMI_GPU_BLOCK_MPIO =      0x0000000000040000,  
  
   AMDSMI_GPU_BLOCK_LAST = AMDSMI_GPU_BLOCK_MPIO,    
   AMDSMI_GPU_BLOCK_RESERVED =  0x8000000000000000
 } amdsmi_gpu_block_t;
  
 typedef enum {
   AMDSMI_RAS_ERR_STATE_NONE = 0,   
   AMDSMI_RAS_ERR_STATE_DISABLED,   
   AMDSMI_RAS_ERR_STATE_PARITY,     
   AMDSMI_RAS_ERR_STATE_SING_C,     
   AMDSMI_RAS_ERR_STATE_MULT_UC,    
   AMDSMI_RAS_ERR_STATE_POISON,     
   AMDSMI_RAS_ERR_STATE_ENABLED,    
  
   AMDSMI_RAS_ERR_STATE_LAST = AMDSMI_RAS_ERR_STATE_ENABLED,
   AMDSMI_RAS_ERR_STATE_INVALID = 0xFFFFFFFF
 } amdsmi_ras_err_state_t;
  
 typedef enum {
   AMDSMI_MEM_TYPE_FIRST = 0,
  
   AMDSMI_MEM_TYPE_VRAM = AMDSMI_MEM_TYPE_FIRST,  
   AMDSMI_MEM_TYPE_VIS_VRAM,                    
   AMDSMI_MEM_TYPE_GTT,                         
  
   AMDSMI_MEM_TYPE_LAST = AMDSMI_MEM_TYPE_GTT
 } amdsmi_memory_type_t;
  
 typedef enum {
   AMDSMI_FREQ_IND_MIN = 0,  
   AMDSMI_FREQ_IND_MAX = 1,  
   AMDSMI_FREQ_IND_INVALID = 0xFFFFFFFF  
 } amdsmi_freq_ind_t;
  
 typedef enum {
   AMDSMI_XGMI_STATUS_NO_ERRORS = 0,
   AMDSMI_XGMI_STATUS_ERROR,
   AMDSMI_XGMI_STATUS_MULTIPLE_ERRORS,
 } amdsmi_xgmi_status_t;
  
 typedef uint64_t amdsmi_bit_field_t;
  
 typedef enum {
   AMDSMI_MEM_PAGE_STATUS_RESERVED = 0,  
   AMDSMI_MEM_PAGE_STATUS_PENDING,       
   AMDSMI_MEM_PAGE_STATUS_UNRESERVABLE   
 } amdsmi_memory_page_status_t;
  
 typedef enum {
   AMDSMI_IOLINK_TYPE_UNDEFINED      = 0,          
   AMDSMI_IOLINK_TYPE_PCIEXPRESS     = 1,          
   AMDSMI_IOLINK_TYPE_XGMI           = 2,          
   AMDSMI_IOLINK_TYPE_NUMIOLINKTYPES,              
   AMDSMI_IOLINK_TYPE_SIZE           = 0xFFFFFFFF  
 } amdsmi_io_link_type_t;
  
 typedef enum {
   AMDSMI_UTILIZATION_COUNTER_FIRST = 0,
   AMDSMI_COARSE_GRAIN_GFX_ACTIVITY  = AMDSMI_UTILIZATION_COUNTER_FIRST,
   AMDSMI_COARSE_GRAIN_MEM_ACTIVITY,    
   AMDSMI_UTILIZATION_COUNTER_LAST = AMDSMI_COARSE_GRAIN_MEM_ACTIVITY
 } amdsmi_utilization_counter_type_t;
  
 typedef enum {
   AMDSMI_AVERAGE_POWER = 0,            
   AMDSMI_CURRENT_POWER,                
   AMDSMI_INVALID_POWER = 0xFFFFFFFF    
 } amdsmi_power_type_t;
  
 typedef struct {
   amdsmi_utilization_counter_type_t type;   
   uint64_t value;                       
 } amdsmi_utilization_counter_t;
  
 typedef struct {
   uint64_t page_address;                  
   uint64_t page_size;                     
   amdsmi_memory_page_status_t status;       
 } amdsmi_retired_page_record_t;
  
 #define AMDSMI_MAX_NUM_POWER_PROFILES (sizeof(amdsmi_bit_field_t) * 8)
  
 typedef struct {
     amdsmi_bit_field_t available_profiles;
  
     amdsmi_power_profile_preset_masks_t current;
  
     uint32_t num_profiles;
 } amdsmi_power_profile_status_t;
  
 typedef struct {
     bool has_deep_sleep;
  
     uint32_t num_supported;
  
     uint32_t current;
  
     uint64_t frequency[AMDSMI_MAX_NUM_FREQUENCIES];
 } amdsmi_frequencies_t;
  
 typedef struct {
   uint32_t policy_id;
   char policy_description[AMDSMI_MAX_NAME];
 } amdsmi_dpm_policy_entry_t;
  
 #define AMDSMI_MAX_NUM_PM_POLICIES 32
  
 typedef struct {
     uint32_t num_supported;
  
     uint32_t current;
  
     amdsmi_dpm_policy_entry_t policies[AMDSMI_MAX_NUM_PM_POLICIES];
 } amdsmi_dpm_policy_t;
  
 typedef struct {
     amdsmi_frequencies_t transfer_rate;
  
     uint32_t lanes[AMDSMI_MAX_NUM_FREQUENCIES];
 } amdsmi_pcie_bandwidth_t;
  
 typedef struct {
     uint32_t year;      
     uint32_t major;     
     uint32_t minor;     
     uint32_t release;   
     const char *build;  
 } amdsmi_version_t;
  
 typedef struct {
     uint64_t frequency;      
     uint64_t voltage;        
 } amdsmi_od_vddc_point_t;
  
 typedef struct {
     amdsmi_range_t freq_range;  
     amdsmi_range_t volt_range;  
 } amdsmi_freq_volt_region_t;
  
 typedef struct {
     amdsmi_od_vddc_point_t vc_points[AMDSMI_NUM_VOLTAGE_CURVE_POINTS];
 } amdsmi_od_volt_curve_t;
  
 typedef struct {
   amdsmi_range_t curr_sclk_range;          
   amdsmi_range_t curr_mclk_range;          
   amdsmi_range_t sclk_freq_limits;         
   amdsmi_range_t mclk_freq_limits;         
  
   amdsmi_od_volt_curve_t curve;
   uint32_t num_regions;                
 } amdsmi_od_volt_freq_data_t;
  
 typedef struct {
   // TODO(amd) Doxygen documents
   // Note: This should match: AMDGpuMetricsHeader_v1_t
   uint16_t      structure_size;
   uint8_t       format_revision;
   uint8_t       content_revision;
 } amd_metrics_table_header_t;
  
 typedef struct {
   // TODO(amd) Doxygen documents
   // Note:  This structure is extended to fit the needs of different GPU metric
   //        versions when exposing data through the structure.
   //        Depending on the version, some data members will hold data, and
   //        some will not. A good example is the set of 'current clocks':
   //          - current_gfxclk, current_socclk, current_vclk0, current_dclk0
   //        These are single-valued data members, up to version 1.3.
   //        For version 1.4 and up these are multi-valued data members (arrays)
   //        and their counterparts;
   //          - current_gfxclks[], current_socclks[], current_vclk0s[],
   //            current_dclk0s[]
   //        will hold the data
   amd_metrics_table_header_t common_header;
  
   /*
    * v1.0 Base
    */
   // Temperature (C)
   uint16_t temperature_edge;
   uint16_t temperature_hotspot;
   uint16_t temperature_mem;
   uint16_t temperature_vrgfx;
   uint16_t temperature_vrsoc;
   uint16_t temperature_vrmem;
  
   // Utilization (%)
   uint16_t average_gfx_activity;
   uint16_t average_umc_activity;    // memory controller
   uint16_t average_mm_activity;     // UVD or VCN
  
   // Power (W) /Energy (15.259uJ per 1ns)
   uint16_t average_socket_power;
   uint64_t energy_accumulator;      // v1 mod. (32->64)
  
   // Driver attached timestamp (in ns)
   uint64_t system_clock_counter;    // v1 mod. (moved from top of struct)
  
   // Average clocks (MHz)
   uint16_t average_gfxclk_frequency;
   uint16_t average_socclk_frequency;
   uint16_t average_uclk_frequency;
   uint16_t average_vclk0_frequency;
   uint16_t average_dclk0_frequency;
   uint16_t average_vclk1_frequency;
   uint16_t average_dclk1_frequency;
  
   // Current clocks (MHz)
   uint16_t current_gfxclk;
   uint16_t current_socclk;
   uint16_t current_uclk;
   uint16_t current_vclk0;
   uint16_t current_dclk0;
   uint16_t current_vclk1;
   uint16_t current_dclk1;
  
   // Throttle status
   uint32_t throttle_status;
  
   // Fans (RPM)
   uint16_t current_fan_speed;
  
   // Link width (number of lanes) /speed (0.1 GT/s)
   uint16_t pcie_link_width;         // v1 mod.(8->16)
   uint16_t pcie_link_speed;         // in 0.1 GT/s; v1 mod. (8->16)
  
  
   /*
    * v1.1 additions
    */
   uint32_t gfx_activity_acc;        // new in v1
   uint32_t mem_activity_acc;        // new in v1
   uint16_t temperature_hbm[AMDSMI_NUM_HBM_INSTANCES];  // new in v1
  
  
   /*
    * v1.2 additions
    */
   // PMFW attached timestamp (10ns resolution)
   uint64_t firmware_timestamp;
  
  
   /*
    * v1.3 additions
    */
   // Voltage (mV)
   uint16_t voltage_soc;
   uint16_t voltage_gfx;
   uint16_t voltage_mem;
  
   // Throttle status
   uint64_t indep_throttle_status;
  
  
   /*
    * v1.4 additions
    */
   // Power (Watts)
   uint16_t current_socket_power;
  
   // Utilization (%)
   uint16_t vcn_activity[AMDSMI_MAX_NUM_VCN];
  
   // Clock Lock Status. Each bit corresponds to clock instance
   uint32_t gfxclk_lock_status;
  
   // XGMI bus width and bitrate (in GB/s)
   uint16_t xgmi_link_width;
   uint16_t xgmi_link_speed;
  
   // PCIe accumulated bandwidth (GB/sec)
   uint64_t pcie_bandwidth_acc;
  
   // PCIe instantaneous bandwidth (GB/sec)
   uint64_t pcie_bandwidth_inst;
  
   // PCIE L0 to recovery state transition accumulated count
   uint64_t pcie_l0_to_recov_count_acc;
  
   // PCIE replay accumulated count
   uint64_t pcie_replay_count_acc;
  
   // PCIE replay rollover accumulated count
   uint64_t pcie_replay_rover_count_acc;
  
   // XGMI accumulated data transfer size (KB)
   uint64_t xgmi_read_data_acc[AMDSMI_MAX_NUM_XGMI_LINKS];
   uint64_t xgmi_write_data_acc[AMDSMI_MAX_NUM_XGMI_LINKS];
  
   // Current clock frequencies (MHz)
   uint16_t current_gfxclks[AMDSMI_MAX_NUM_GFX_CLKS];
   uint16_t current_socclks[AMDSMI_MAX_NUM_CLKS];
   uint16_t current_vclk0s[AMDSMI_MAX_NUM_CLKS];
   uint16_t current_dclk0s[AMDSMI_MAX_NUM_CLKS];
  
    /*
    * v1.5 additions
    */
   // JPEG activity % per AID
   uint16_t jpeg_activity[AMDSMI_MAX_NUM_JPEG];
  
   // PCIE NAK sent accumulated count
   uint32_t pcie_nak_sent_count_acc;
  
   // PCIE NAK received accumulated count
   uint32_t pcie_nak_rcvd_count_acc;
 } amdsmi_gpu_metrics_t;
  
  
 #define  MAX_AMDSMI_NAME_LENGTH 64
  
 typedef struct {
     char name[MAX_AMDSMI_NAME_LENGTH];     
     uint64_t value;   
 } amdsmi_name_value_t;
  
 typedef enum {
   AMDSMI_REG_XGMI,
   AMDSMI_REG_WAFL,
   AMDSMI_REG_PCIE,
   AMDSMI_REG_USR,
   AMDSMI_REG_USR1,
 } amdsmi_reg_type_t;
  
 typedef struct {
   uint32_t ras_eeprom_version;
   // PARITY error(bit 0), Single Bit correctable (bit1),
   // Double bit error detection (bit2), Poison (bit 3).
   uint32_t ecc_correction_schema_flag;    
 } amdsmi_ras_feature_t;
  
 typedef struct {
   uint64_t correctable_count;   
   uint64_t uncorrectable_count;  
   uint64_t deferred_count;  
   uint64_t reserved[5];
 } amdsmi_error_count_t;
  
 typedef struct {
     uint32_t process_id;      
     uint32_t pasid;           
     uint64_t vram_usage;      
     uint64_t sdma_usage;      
     uint32_t cu_occupancy;    
 } amdsmi_process_info_t;
  
 #define AMDSMI_DEFAULT_VARIANT 0xFFFFFFFFFFFFFFFF
  
 #ifdef ENABLE_ESMI_LIB
 typedef struct {
         uint8_t debug;      
         uint8_t minor;      
         uint8_t major;      
         uint8_t unused;     
 } amdsmi_smu_fw_version_t;
  
 typedef struct {
         uint32_t max_bw;    
         uint32_t utilized_bw;   
         uint32_t utilized_pct;  
 } amdsmi_ddr_bw_metrics_t;
  
 typedef struct {
     uint8_t range : 3;  
     uint8_t ref_rate : 1;   
 } amdsmi_temp_range_refresh_rate_t;
  
 typedef struct {
     uint16_t power : 15;            
     uint16_t update_rate : 9;       
     uint8_t dimm_addr;              
 } amdsmi_dimm_power_t;
  
 typedef struct {
     uint16_t sensor : 11;           
     uint16_t update_rate : 9;       
     uint8_t dimm_addr;              
     float temp;         
 } amdsmi_dimm_thermal_t;
  
 typedef enum {
     AGG_BW0 = 1, 
     RD_BW0 = 2,      
     WR_BW0 = 4       
 } amdsmi_io_bw_encoding_t;
  
 typedef struct {
     amdsmi_io_bw_encoding_t bw_type;         
     char *link_name;            
 } amdsmi_link_id_bw_type_t;
  
 typedef struct {
     uint8_t max_dpm_level;          
     uint8_t min_dpm_level;          
 } amdsmi_dpm_level_t;
  
 typedef struct __attribute__((__packed__)){
     uint32_t accumulation_counter;
  
     /* TEMPERATURE */
     uint32_t max_socket_temperature;
     uint32_t max_vr_temperature;
     uint32_t max_hbm_temperature;
     uint64_t max_socket_temperature_acc;
     uint64_t max_vr_temperature_acc;
     uint64_t max_hbm_temperature_acc;
  
     /* POWER */
     uint32_t socket_power_limit;
     uint32_t max_socket_power_limit;
     uint32_t socket_power;
  
     /* ENERGY */
     uint64_t timestamp;
     uint64_t socket_energy_acc;
     uint64_t ccd_energy_acc;
     uint64_t xcd_energy_acc;
     uint64_t aid_energy_acc;
     uint64_t hbm_energy_acc;
  
     /* FREQUENCY */
     uint32_t cclk_frequency_limit;
     uint32_t gfxclk_frequency_limit;
     uint32_t fclk_frequency;
     uint32_t uclk_frequency;
     uint32_t socclk_frequency[4];
     uint32_t vclk_frequency[4];
     uint32_t dclk_frequency[4];
     uint32_t lclk_frequency[4];
     uint64_t gfxclk_frequency_acc[8];
     uint64_t cclk_frequency_acc[96];
  
     /* FREQUENCY RANGE */
     uint32_t max_cclk_frequency;
     uint32_t min_cclk_frequency;
     uint32_t max_gfxclk_frequency;
     uint32_t min_gfxclk_frequency;
     uint32_t fclk_frequency_table[4];
     uint32_t uclk_frequency_table[4];
     uint32_t socclk_frequency_table[4];
     uint32_t vclk_frequency_table[4];
     uint32_t dclk_frequency_table[4];
     uint32_t lclk_frequency_table[4];
     uint32_t max_lclk_dpm_range;
     uint32_t min_lclk_dpm_range;
  
     /* XGMI */
     uint32_t xgmi_width;
     uint32_t xgmi_bitrate;
     uint64_t xgmi_read_bandwidth_acc[8];
     uint64_t xgmi_write_bandwidth_acc[8];
  
     /* ACTIVITY */
     uint32_t socket_c0_residency;
     uint32_t socket_gfx_busy;
     uint32_t dram_bandwidth_utilization;
     uint64_t socket_c0_residency_acc;
     uint64_t socket_gfx_busy_acc;
     uint64_t dram_bandwidth_acc;
     uint32_t max_dram_bandwidth;
     uint64_t dram_bandwidth_utilization_acc;
     uint64_t pcie_bandwidth_acc[4];
  
     /* THROTTLERS */
     uint32_t prochot_residency_acc;
     uint32_t ppt_residency_acc;
     uint32_t socket_thm_residency_acc;
     uint32_t vr_thm_residency_acc;
     uint32_t hbm_thm_residency_acc;
     uint32_t spare;
  
     /* New items at the end to maintain driver compatibility */
     uint32_t gfxclk_frequency[8];
 } amdsmi_hsmp_metrics_table_t;
  
 static char* const amdsmi_hsmp_freqlimit_src_names[] = {
         "cHTC-Active",
         "PROCHOT",
         "TDC limit",
         "PPT Limit",
         "OPN Max",
         "Reliability Limit",
         "APML Agent",
         "HSMP Agent"
 };
 #endif
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_init(uint64_t init_flags);
  
 amdsmi_status_t amdsmi_shut_down(void);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count,
                 amdsmi_socket_handle* socket_handles);
  
 #ifdef ENABLE_ESMI_LIB
 amdsmi_status_t amdsmi_get_cpusocket_handles(uint32_t *socket_count,
                 amdsmi_cpusocket_handle* socket_handles);
 #endif
  
 amdsmi_status_t amdsmi_get_socket_info(
                 amdsmi_socket_handle socket_handle,
                 size_t len, char *name);
  
 #ifdef ENABLE_ESMI_LIB
 amdsmi_status_t amdsmi_get_processor_info(
                 amdsmi_processor_handle processor_handle,
                 size_t len, char *name);
  
 amdsmi_status_t amdsmi_get_processor_count_from_handles(amdsmi_processor_handle* processor_handles,
                                                         uint32_t* processor_count, uint32_t* nr_cpusockets,
                                                         uint32_t* nr_cpucores, uint32_t* nr_gpus);
  
 amdsmi_status_t amdsmi_get_processor_handles_by_type(amdsmi_socket_handle socket_handle,
                                                      processor_type_t processor_type,
                                                      amdsmi_processor_handle* processor_handles,
                                                      uint32_t* processor_count);
 #endif
  
 amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle,
                                     uint32_t *processor_count,
                                     amdsmi_processor_handle* processor_handles);
  
 #ifdef ENABLE_ESMI_LIB
 amdsmi_status_t amdsmi_get_cpucore_handles(amdsmi_cpusocket_handle socket_handle,
                                     uint32_t *processor_count,
                                     amdsmi_processor_handle* processor_handles);
 #endif
  
 amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle,
               processor_type_t* processor_type);
  
 amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf,
               amdsmi_processor_handle* processor_handle);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_gpu_id(amdsmi_processor_handle processor_handle, uint16_t *id);
  
 amdsmi_status_t amdsmi_get_gpu_revision(amdsmi_processor_handle processor_handle, uint16_t *revision);
  
 amdsmi_status_t amdsmi_get_gpu_vendor_name(amdsmi_processor_handle processor_handle, char *name,
                                                                   size_t len);
  
 amdsmi_status_t amdsmi_get_gpu_vram_vendor(amdsmi_processor_handle processor_handle, char *brand,
                                                                 uint32_t len);
  
 amdsmi_status_t amdsmi_get_gpu_subsystem_id(amdsmi_processor_handle processor_handle, uint16_t *id);
  
 amdsmi_status_t
 amdsmi_get_gpu_subsystem_name(amdsmi_processor_handle processor_handle, char *name, size_t len);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_pci_bandwidth(amdsmi_processor_handle processor_handle,
                               amdsmi_pcie_bandwidth_t *bandwidth);
  
 amdsmi_status_t amdsmi_get_gpu_bdf_id(amdsmi_processor_handle processor_handle, uint64_t *bdfid);
  
 amdsmi_status_t amdsmi_get_gpu_topo_numa_affinity(amdsmi_processor_handle processor_handle,
                                                     int32_t *numa_node);
  
 amdsmi_status_t amdsmi_get_gpu_pci_throughput(amdsmi_processor_handle processor_handle, uint64_t *sent,
                                     uint64_t *received, uint64_t *max_pkt_sz);
  
 amdsmi_status_t amdsmi_get_gpu_pci_replay_counter(amdsmi_processor_handle processor_handle,
                                                            uint64_t *counter);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_set_gpu_pci_bandwidth(amdsmi_processor_handle processor_handle,
                                               uint64_t bw_bitmask);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_energy_count(amdsmi_processor_handle processor_handle, uint64_t *power,
                           float *counter_resolution, uint64_t *timestamp);
  
 /*****************************************************************************/
 amdsmi_status_t
  amdsmi_set_power_cap(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, uint64_t cap);
  
 amdsmi_status_t
  amdsmi_set_gpu_power_profile(amdsmi_processor_handle processor_handle, uint32_t reserved,
                                    amdsmi_power_profile_preset_masks_t profile);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_memory_total(amdsmi_processor_handle processor_handle, amdsmi_memory_type_t mem_type,
                                                              uint64_t *total);
  
 amdsmi_status_t
 amdsmi_get_gpu_memory_usage(amdsmi_processor_handle processor_handle, amdsmi_memory_type_t mem_type,
                                                               uint64_t *used);
  
 amdsmi_status_t
 amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *num_pages,
                               amdsmi_retired_page_record_t *info);
  
 amdsmi_status_t amdsmi_get_gpu_ras_feature_info(
   amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature);
  
  
 amdsmi_status_t
 amdsmi_get_gpu_ras_block_features_enabled(amdsmi_processor_handle processor_handle,
                                             amdsmi_gpu_block_t block,
                                             amdsmi_ras_err_state_t *state);
  
 amdsmi_status_t
 amdsmi_get_gpu_memory_reserved_pages(amdsmi_processor_handle processor_handle,
                                       uint32_t *num_pages,
                                       amdsmi_retired_page_record_t *records);
  
 amdsmi_status_t amdsmi_get_gpu_fan_rpms(amdsmi_processor_handle processor_handle,
                                           uint32_t sensor_ind, int64_t *speed);
  
 amdsmi_status_t amdsmi_get_gpu_fan_speed(amdsmi_processor_handle processor_handle,
                                         uint32_t sensor_ind, int64_t *speed);
  
 amdsmi_status_t amdsmi_get_gpu_fan_speed_max(amdsmi_processor_handle processor_handle,
                                     uint32_t sensor_ind, uint64_t *max_speed);
  
 amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle,
                       amdsmi_temperature_type_t sensor_type,
                       amdsmi_temperature_metric_t metric, int64_t *temperature);
  
 amdsmi_status_t amdsmi_get_gpu_cache_info(
       amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info);
  
 amdsmi_status_t amdsmi_get_gpu_volt_metric(amdsmi_processor_handle processor_handle,
                                amdsmi_voltage_type_t sensor_type,
                               amdsmi_voltage_metric_t metric, int64_t *voltage);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_reset_gpu_fan(amdsmi_processor_handle processor_handle, uint32_t sensor_ind);
  
 amdsmi_status_t amdsmi_set_gpu_fan_speed(amdsmi_processor_handle processor_handle,
       uint32_t sensor_ind, uint64_t speed);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_utilization_count(amdsmi_processor_handle processor_handle,
                 amdsmi_utilization_counter_t utilization_counters[],
                 uint32_t count,
                 uint64_t *timestamp);
  
 amdsmi_status_t amdsmi_get_gpu_perf_level(amdsmi_processor_handle processor_handle,
                                                  amdsmi_dev_perf_level_t *perf);
  
 amdsmi_status_t
 amdsmi_set_gpu_perf_determinism_mode(amdsmi_processor_handle processor_handle, uint64_t clkvalue);
  
 amdsmi_status_t amdsmi_get_gpu_overdrive_level(amdsmi_processor_handle processor_handle,
                                                 uint32_t *od);
  
 amdsmi_status_t amdsmi_get_clk_freq(amdsmi_processor_handle processor_handle,
                              amdsmi_clk_type_t clk_type, amdsmi_frequencies_t *f);
  
 amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle);
  
 amdsmi_status_t amdsmi_get_gpu_od_volt_info(amdsmi_processor_handle processor_handle,
                                                amdsmi_od_volt_freq_data_t *odv);
  
 amdsmi_status_t
 amdsmi_get_gpu_metrics_header_info(amdsmi_processor_handle processor_handle, amd_metrics_table_header_t* header_value);
  
 amdsmi_status_t amdsmi_get_gpu_metrics_info(amdsmi_processor_handle processor_handle,
                                             amdsmi_gpu_metrics_t *pgpu_metrics);
  
 amdsmi_status_t amdsmi_get_gpu_pm_metrics_info(
                       amdsmi_processor_handle processor_handle,
                       amdsmi_name_value_t** pm_metrics,
                       uint32_t *num_of_metrics);
  
 amdsmi_status_t amdsmi_get_gpu_reg_table_info(
                       amdsmi_processor_handle processor_handle,
                       amdsmi_reg_type_t reg_type,
                       amdsmi_name_value_t** reg_metrics,
                       uint32_t *num_of_metrics);
  
 amdsmi_status_t amdsmi_set_gpu_clk_range(amdsmi_processor_handle processor_handle,
                                           uint64_t minclkvalue,
                                           uint64_t maxclkvalue,
                                           amdsmi_clk_type_t clkType);
  
 amdsmi_status_t amdsmi_set_gpu_od_clk_info(amdsmi_processor_handle processor_handle,
                                         amdsmi_freq_ind_t level,
                                         uint64_t clkvalue,
                                         amdsmi_clk_type_t clkType);
  
 amdsmi_status_t amdsmi_set_gpu_od_volt_info(amdsmi_processor_handle processor_handle,
                                               uint32_t vpoint,
                                               uint64_t clkvalue,
                                               uint64_t voltvalue);
  
 amdsmi_status_t amdsmi_get_gpu_od_volt_curve_regions(amdsmi_processor_handle processor_handle,
                       uint32_t *num_regions, amdsmi_freq_volt_region_t *buffer);
  
 amdsmi_status_t
  amdsmi_get_gpu_power_profile_presets(amdsmi_processor_handle processor_handle, uint32_t sensor_ind,
                                          amdsmi_power_profile_status_t *status);
  
 /*****************************************************************************/
 amdsmi_status_t
  amdsmi_set_gpu_perf_level(amdsmi_processor_handle processor_handle, amdsmi_dev_perf_level_t perf_lvl);
  
 amdsmi_status_t amdsmi_set_gpu_overdrive_level(amdsmi_processor_handle processor_handle, uint32_t od);
  
 amdsmi_status_t amdsmi_set_clk_freq(amdsmi_processor_handle processor_handle,
                              amdsmi_clk_type_t clk_type, uint64_t freq_bitmask);
  
 amdsmi_status_t amdsmi_get_dpm_policy(amdsmi_processor_handle processor_handle,
                              amdsmi_dpm_policy_t* policy);
  
 amdsmi_status_t amdsmi_set_dpm_policy(amdsmi_processor_handle processor_handle,
                              uint32_t policy_id);
  
 amdsmi_status_t amdsmi_get_xgmi_plpd(amdsmi_processor_handle processor_handle,
                              amdsmi_dpm_policy_t* xgmi_plpd);
  
 amdsmi_status_t amdsmi_set_xgmi_plpd(amdsmi_processor_handle processor_handle,
                              uint32_t plpd_id);
  
  
 amdsmi_status_t amdsmi_get_gpu_process_isolation(amdsmi_processor_handle processor_handle,
                              uint32_t* pisolate);
  
 amdsmi_status_t amdsmi_set_gpu_process_isolation(amdsmi_processor_handle processor_handle,
                              uint32_t pisolate);
  
 amdsmi_status_t amdsmi_set_gpu_clear_sram_data(amdsmi_processor_handle processor_handle,
                   uint32_t sclean);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_lib_version(amdsmi_version_t *version);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle,
                               amdsmi_gpu_block_t block, amdsmi_error_count_t *ec);
  
 amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle,
                                                     uint64_t *enabled_blocks);
  
 amdsmi_status_t amdsmi_get_gpu_ecc_status(amdsmi_processor_handle processor_handle,
                                                   amdsmi_gpu_block_t block,
                                                   amdsmi_ras_err_state_t *state);
  
 amdsmi_status_t
 amdsmi_status_code_to_string(amdsmi_status_t status, const char **status_string);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_gpu_counter_group_supported(amdsmi_processor_handle processor_handle, amdsmi_event_group_t group);
  
 amdsmi_status_t
 amdsmi_gpu_create_counter(amdsmi_processor_handle processor_handle, amdsmi_event_type_t type,
                                             amdsmi_event_handle_t *evnt_handle);
  
 amdsmi_status_t
 amdsmi_gpu_destroy_counter(amdsmi_event_handle_t evnt_handle);
  
 amdsmi_status_t
 amdsmi_gpu_control_counter(amdsmi_event_handle_t evt_handle,
                                   amdsmi_counter_command_t cmd, void *cmd_args);
  
 amdsmi_status_t
 amdsmi_gpu_read_counter(amdsmi_event_handle_t evt_handle,
                     amdsmi_counter_value_t *value);
  
 amdsmi_status_t
  amdsmi_get_gpu_available_counters(amdsmi_processor_handle processor_handle,
                                  amdsmi_event_group_t grp, uint32_t *available);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_compute_process_info(amdsmi_process_info_t *procs, uint32_t *num_items);
  
 amdsmi_status_t
 amdsmi_get_gpu_compute_process_info_by_pid(uint32_t pid, amdsmi_process_info_t *proc);
  
 amdsmi_status_t
 amdsmi_get_gpu_compute_process_gpus(uint32_t pid, uint32_t *dv_indices,
                                                        uint32_t *num_devices);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_gpu_xgmi_error_status(amdsmi_processor_handle processor_handle, amdsmi_xgmi_status_t *status);
  
 amdsmi_status_t
 amdsmi_reset_gpu_xgmi_error(amdsmi_processor_handle processor_handle);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_link_metrics(amdsmi_processor_handle processor_handle,
           amdsmi_link_metrics_t *link_metrics);
  
 amdsmi_status_t
 amdsmi_topo_get_numa_node_number(amdsmi_processor_handle processor_handle, uint32_t *numa_node);
  
 amdsmi_status_t
 amdsmi_topo_get_link_weight(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst,
                           uint64_t *weight);
  
 amdsmi_status_t
  amdsmi_get_minmax_bandwidth_between_processors(amdsmi_processor_handle processor_handle_src,
                                                   amdsmi_processor_handle processor_handle_dst,
                                                   uint64_t *min_bandwidth,
                                                   uint64_t *max_bandwidth);
  
 amdsmi_status_t
 amdsmi_topo_get_link_type(amdsmi_processor_handle processor_handle_src,
                         amdsmi_processor_handle processor_handle_dst,
                         uint64_t *hops, amdsmi_io_link_type_t *type);
  
 amdsmi_status_t
 amdsmi_is_P2P_accessible(amdsmi_processor_handle processor_handle_src,
                           amdsmi_processor_handle processor_handle_dst,
                           bool *accessible);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_compute_partition(amdsmi_processor_handle processor_handle,
                                   char *compute_partition, uint32_t len);
  
 amdsmi_status_t
 amdsmi_set_gpu_compute_partition(amdsmi_processor_handle processor_handle,
                                   amdsmi_compute_partition_type_t compute_partition);
  
 amdsmi_status_t amdsmi_reset_gpu_compute_partition(amdsmi_processor_handle processor_handle);
   // end of compute_partition
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_memory_partition(amdsmi_processor_handle processor_handle,
                                   char *memory_partition, uint32_t len);
  
 amdsmi_status_t
 amdsmi_set_gpu_memory_partition(amdsmi_processor_handle processor_handle,
                                   amdsmi_memory_partition_type_t memory_partition);
  
 amdsmi_status_t amdsmi_reset_gpu_memory_partition(amdsmi_processor_handle processor_handle);
   // end of memory_partition
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_init_gpu_event_notification(amdsmi_processor_handle processor_handle);
  
 amdsmi_status_t
  amdsmi_set_gpu_event_notification_mask(amdsmi_processor_handle processor_handle, uint64_t mask);
  
 amdsmi_status_t
  amdsmi_get_gpu_event_notification(int timeout_ms,
                      uint32_t *num_elem, amdsmi_evt_notification_data_t *data);
  
 amdsmi_status_t amdsmi_stop_gpu_event_notification(amdsmi_processor_handle processor_handle);
  
 amdsmi_status_t
 amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);
  
 amdsmi_status_t
 amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info);
  
 amdsmi_status_t amdsmi_get_gpu_vram_info(
           amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info);
  
 amdsmi_status_t
 amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info);
  
 amdsmi_status_t
 amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind,
           amdsmi_power_cap_info_t *info);
  
 amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle,
           amdsmi_pcie_info_t *info);
  
 amdsmi_status_t
 amdsmi_get_xgmi_info(amdsmi_processor_handle processor_handle, amdsmi_xgmi_info_t *info);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info);
  
 amdsmi_status_t
 amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info);
  
 amdsmi_status_t
 amdsmi_get_power_info(amdsmi_processor_handle processor_handle, amdsmi_power_info_t *info);
  
 amdsmi_status_t
 amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled);
  
 amdsmi_status_t
 amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info);
  
 amdsmi_status_t
 amdsmi_get_gpu_vram_usage(amdsmi_processor_handle processor_handle, amdsmi_vram_usage_t *info);
  
  
 /*****************************************************************************/
     //  Note: If the reserved size for processes is smaller than the number of
     //        actual processes running. The AMDSMI_STATUS_OUT_OF_RESOURCES is
     //        an indication the caller should handle the situation (resize).
     //        The max_processes is always changed to reflect the actual size of
     //        list of processes running, so the caller knows where it is at.
     //
 amdsmi_status_t
 amdsmi_get_gpu_process_list(amdsmi_processor_handle processor_handle, uint32_t *max_processes, amdsmi_proc_info_t *list);
  
 /*****************************************************************************/
 amdsmi_status_t
 amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec);
  
 #ifdef ENABLE_ESMI_LIB
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_cpu_core_energy(amdsmi_processor_handle processor_handle,
                                            uint64_t *penergy);
  
 amdsmi_status_t amdsmi_get_cpu_socket_energy(amdsmi_processor_handle processor_handle,
                                              uint64_t *penergy);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_cpu_smu_fw_version(amdsmi_processor_handle processor_handle,
                                               amdsmi_smu_fw_version_t *amdsmi_smu_fw);
  
 amdsmi_status_t amdsmi_get_cpu_hsmp_proto_ver(amdsmi_processor_handle processor_handle,
                                               uint32_t *proto_ver);
  
 amdsmi_status_t amdsmi_get_cpu_prochot_status(amdsmi_processor_handle processor_handle,
                                               uint32_t *prochot);
  
 amdsmi_status_t amdsmi_get_cpu_fclk_mclk(amdsmi_processor_handle processor_handle,
                                          uint32_t *fclk, uint32_t *mclk);
  
 amdsmi_status_t amdsmi_get_cpu_cclk_limit(amdsmi_processor_handle processor_handle,
                                           uint32_t *cclk);
  
 amdsmi_status_t amdsmi_get_cpu_socket_current_active_freq_limit(amdsmi_processor_handle processor_handle,
                                                                 uint16_t *freq, char **src_type);
  
 amdsmi_status_t amdsmi_get_cpu_socket_freq_range(amdsmi_processor_handle processor_handle,
                                                  uint16_t *fmax, uint16_t *fmin);
  
 amdsmi_status_t amdsmi_get_cpu_core_current_freq_limit(amdsmi_processor_handle processor_handle,
                                                        uint32_t *freq);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_cpu_socket_power(amdsmi_processor_handle processor_handle,
                                             uint32_t *ppower);
  
 amdsmi_status_t amdsmi_get_cpu_socket_power_cap(amdsmi_processor_handle processor_handle,
                                                 uint32_t *pcap);
  
 amdsmi_status_t amdsmi_get_cpu_socket_power_cap_max(amdsmi_processor_handle processor_handle,
                                                     uint32_t *pmax);
  
 amdsmi_status_t amdsmi_get_cpu_pwr_svi_telemetry_all_rails(amdsmi_processor_handle processor_handle,
                                                            uint32_t *power);
  
 amdsmi_status_t amdsmi_set_cpu_socket_power_cap(amdsmi_processor_handle processor_handle,
                                                 uint32_t pcap);
  
 amdsmi_status_t amdsmi_set_cpu_pwr_efficiency_mode(amdsmi_processor_handle processor_handle,
                                                    uint8_t mode);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_cpu_core_boostlimit(amdsmi_processor_handle processor_handle,
                                                uint32_t *pboostlimit);
  
 amdsmi_status_t amdsmi_get_cpu_socket_c0_residency(amdsmi_processor_handle processor_handle,
                                                    uint32_t *pc0_residency);
  
 amdsmi_status_t amdsmi_set_cpu_core_boostlimit(amdsmi_processor_handle processor_handle,
                                                uint32_t boostlimit);
  
 amdsmi_status_t amdsmi_set_cpu_socket_boostlimit(amdsmi_processor_handle processor_handle,
                                                  uint32_t boostlimit);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_cpu_ddr_bw(amdsmi_processor_handle processor_handle,
                                       amdsmi_ddr_bw_metrics_t *ddr_bw);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_cpu_socket_temperature(amdsmi_processor_handle processor_handle,
                                                   uint32_t *ptmon);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_cpu_dimm_temp_range_and_refresh_rate(amdsmi_processor_handle processor_handle,
                                                                 uint8_t dimm_addr,
                                                                 amdsmi_temp_range_refresh_rate_t *rate);
  
 amdsmi_status_t amdsmi_get_cpu_dimm_power_consumption(amdsmi_processor_handle processor_handle,
                                                       uint8_t dimm_addr,
                                                       amdsmi_dimm_power_t *dimm_pow);
  
 amdsmi_status_t amdsmi_get_cpu_dimm_thermal_sensor(amdsmi_processor_handle processor_handle,
                                                    uint8_t dimm_addr,
                                                    amdsmi_dimm_thermal_t *dimm_temp);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_set_cpu_xgmi_width(amdsmi_processor_handle processor_handle,
                                           uint8_t min, uint8_t max);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_set_cpu_gmi3_link_width_range(amdsmi_processor_handle processor_handle,
                                                      uint8_t min_link_width, uint8_t max_link_width);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_cpu_apb_enable(amdsmi_processor_handle processor_handle);
  
 amdsmi_status_t amdsmi_cpu_apb_disable(amdsmi_processor_handle processor_handle,
                                        uint8_t pstate);
  
 amdsmi_status_t amdsmi_set_cpu_socket_lclk_dpm_level(amdsmi_processor_handle processor_handle,
                                                      uint8_t nbio_id, uint8_t min, uint8_t max);
  
 amdsmi_status_t amdsmi_get_cpu_socket_lclk_dpm_level(amdsmi_processor_handle processor_handle,
                                                      uint8_t nbio_id, amdsmi_dpm_level_t *nbio);
  
 amdsmi_status_t amdsmi_set_cpu_pcie_link_rate(amdsmi_processor_handle processor_handle,
                                               uint8_t rate_ctrl, uint8_t *prev_mode);
  
 amdsmi_status_t amdsmi_set_cpu_df_pstate_range(amdsmi_processor_handle processor_handle,
                                                uint8_t max_pstate, uint8_t min_pstate);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_cpu_current_io_bandwidth(amdsmi_processor_handle processor_handle,
                                                     amdsmi_link_id_bw_type_t link, uint32_t *io_bw);
  
 amdsmi_status_t amdsmi_get_cpu_current_xgmi_bw(amdsmi_processor_handle processor_handle,
                                                amdsmi_link_id_bw_type_t link, uint32_t *xgmi_bw);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_get_hsmp_metrics_table_version(amdsmi_processor_handle processor_handle,
                                                  uint32_t *metrics_version);
  
 amdsmi_status_t amdsmi_get_hsmp_metrics_table(amdsmi_processor_handle processor_handle,
                                          amdsmi_hsmp_metrics_table_t *metrics_table);
  
 /*****************************************************************************/
 amdsmi_status_t amdsmi_first_online_core_on_cpu_socket(amdsmi_processor_handle processor_handle,
                                                        uint32_t *pcore_ind);
  
 amdsmi_status_t amdsmi_get_cpu_family(uint32_t *cpu_family);
  
 amdsmi_status_t amdsmi_get_cpu_model(uint32_t *cpu_model);
  
 amdsmi_status_t amdsmi_get_esmi_err_msg(amdsmi_status_t status, const char **status_string);
 #endif
 #ifdef __cplusplus
 }
 #endif  // __cplusplus
 #endif  // INCLUDE_AMDSMI_H_