#include <hip_deprecated.h>

Collaboration diagram for hipDeviceProp_tR0000:

Data Fields
char	name [256]
	Device name. More...

size_t	totalGlobalMem
	Size of global memory region (in bytes). More...

size_t	sharedMemPerBlock
	Size of shared memory region (in bytes). More...

int	regsPerBlock
	Registers per block. More...

int	warpSize
	Warp size. More...

int	maxThreadsPerBlock
	Max work items per work group or workgroup max size. More...

int	maxThreadsDim [3]
	Max number of threads in each dimension (XYZ) of a block. More...

int	maxGridSize [3]
	Max grid dimensions (XYZ). More...

int	clockRate
	Max clock frequency of the multiProcessors in khz. More...

int	memoryClockRate
	Max global memory clock frequency in khz. More...

int	memoryBusWidth
	Global memory bus width in bits. More...

size_t	totalConstMem
	Size of shared memory region (in bytes). More...

int	major

int	minor

int	multiProcessorCount
	Number of multi-processors (compute units). More...

int	l2CacheSize
	L2 cache size. More...

int	maxThreadsPerMultiProcessor
	Maximum resident threads per multi-processor. More...

int	computeMode
	Compute mode. More...

int	clockInstructionRate

hipDeviceArch_t	arch
	Architectural feature flags. New for HIP. More...

int	concurrentKernels
	Device can possibly execute multiple kernels concurrently. More...

int	pciDomainID
	PCI Domain ID. More...

int	pciBusID
	PCI Bus ID. More...

int	pciDeviceID
	PCI Device ID. More...

size_t	maxSharedMemoryPerMultiProcessor
	Maximum Shared Memory Per Multiprocessor. More...

int	isMultiGpuBoard
	1 if device is on a multi-GPU board, 0 if not. More...

int	canMapHostMemory
	Check whether HIP can map host memory. More...

int	gcnArch
	DEPRECATED: use gcnArchName instead. More...

char	gcnArchName [256]
	AMD GCN Arch Name. More...

int	integrated
	APU vs dGPU. More...

int	cooperativeLaunch
	HIP device supports cooperative launch. More...

int	cooperativeMultiDeviceLaunch

int	maxTexture1DLinear
	Maximum size for 1D textures bound to linear memory. More...

int	maxTexture1D
	Maximum number of elements in 1D images. More...

int	maxTexture2D [2]
	Maximum dimensions (width, height) of 2D images, in image elements. More...

int	maxTexture3D [3]

unsigned int *	hdpMemFlushCntl
	Addres of HDP_MEM_COHERENCY_FLUSH_CNTL register. More...

unsigned int *	hdpRegFlushCntl
	Addres of HDP_REG_COHERENCY_FLUSH_CNTL register. More...

size_t	memPitch
	Maximum pitch in bytes allowed by memory copies. More...

size_t	textureAlignment
	Alignment requirement for textures. More...

size_t	texturePitchAlignment

int	kernelExecTimeoutEnabled
	Run time limit for kernels executed on the device. More...

int	ECCEnabled
	Device has ECC support enabled. More...

int	tccDriver
	1:If device is Tesla device using TCC driver, else 0 More...

int	cooperativeMultiDeviceUnmatchedFunc

int	cooperativeMultiDeviceUnmatchedGridDim

int	cooperativeMultiDeviceUnmatchedBlockDim

int	cooperativeMultiDeviceUnmatchedSharedMem

int	isLargeBar
	1: if it is a large PCI bar device, else 0 More...

int	asicRevision
	Revision of the GPU in this device. More...

int	managedMemory
	Device supports allocating managed memory on this system. More...

int	directManagedMemAccessFromHost

int	concurrentManagedAccess

int	pageableMemoryAccess

int	pageableMemoryAccessUsesHostPageTables

Field Documentation

◆ arch

hipDeviceArch_t hipDeviceProp_tR0000::arch

Architectural feature flags. New for HIP.

◆ asicRevision

int hipDeviceProp_tR0000::asicRevision

Revision of the GPU in this device.

◆ canMapHostMemory

int hipDeviceProp_tR0000::canMapHostMemory

Check whether HIP can map host memory.

◆ clockInstructionRate

int hipDeviceProp_tR0000::clockInstructionRate

Frequency in khz of the timer used by the device-side "clock*" instructions. New for HIP.

◆ clockRate

int hipDeviceProp_tR0000::clockRate

Max clock frequency of the multiProcessors in khz.

◆ computeMode

int hipDeviceProp_tR0000::computeMode

Compute mode.

◆ concurrentKernels

int hipDeviceProp_tR0000::concurrentKernels

Device can possibly execute multiple kernels concurrently.

◆ concurrentManagedAccess

int hipDeviceProp_tR0000::concurrentManagedAccess

Device can coherently access managed memory concurrently with the CPU

◆ cooperativeLaunch

int hipDeviceProp_tR0000::cooperativeLaunch

HIP device supports cooperative launch.

◆ cooperativeMultiDeviceLaunch

int hipDeviceProp_tR0000::cooperativeMultiDeviceLaunch

HIP device supports cooperative launch on multiple devices

◆ cooperativeMultiDeviceUnmatchedBlockDim

int hipDeviceProp_tR0000::cooperativeMultiDeviceUnmatchedBlockDim

HIP device supports cooperative launch on multiple devices with unmatched block dimensions

◆ cooperativeMultiDeviceUnmatchedFunc

int hipDeviceProp_tR0000::cooperativeMultiDeviceUnmatchedFunc

HIP device supports cooperative launch on multiple devices with unmatched functions

◆ cooperativeMultiDeviceUnmatchedGridDim

int hipDeviceProp_tR0000::cooperativeMultiDeviceUnmatchedGridDim

HIP device supports cooperative launch on multiple devices with unmatched grid dimensions

◆ cooperativeMultiDeviceUnmatchedSharedMem

int hipDeviceProp_tR0000::cooperativeMultiDeviceUnmatchedSharedMem

HIP device supports cooperative launch on multiple devices with unmatched shared memories

◆ directManagedMemAccessFromHost

int hipDeviceProp_tR0000::directManagedMemAccessFromHost

Host can directly access managed memory on the device without migration

◆ ECCEnabled

int hipDeviceProp_tR0000::ECCEnabled

Device has ECC support enabled.

◆ gcnArch

int hipDeviceProp_tR0000::gcnArch

DEPRECATED: use gcnArchName instead.

◆ gcnArchName

char hipDeviceProp_tR0000::gcnArchName[256]

AMD GCN Arch Name.

◆ hdpMemFlushCntl

unsigned int* hipDeviceProp_tR0000::hdpMemFlushCntl

Addres of HDP_MEM_COHERENCY_FLUSH_CNTL register.

◆ hdpRegFlushCntl

unsigned int* hipDeviceProp_tR0000::hdpRegFlushCntl

Addres of HDP_REG_COHERENCY_FLUSH_CNTL register.

◆ integrated

int hipDeviceProp_tR0000::integrated

APU vs dGPU.

◆ isLargeBar

int hipDeviceProp_tR0000::isLargeBar

1: if it is a large PCI bar device, else 0

◆ isMultiGpuBoard

int hipDeviceProp_tR0000::isMultiGpuBoard

1 if device is on a multi-GPU board, 0 if not.

◆ kernelExecTimeoutEnabled

int hipDeviceProp_tR0000::kernelExecTimeoutEnabled

Run time limit for kernels executed on the device.

◆ l2CacheSize

int hipDeviceProp_tR0000::l2CacheSize

L2 cache size.

◆ major

int hipDeviceProp_tR0000::major

Major compute capability. On HCC, this is an approximation and features may differ from CUDA CC. See the arch feature flags for portable ways to query feature caps.

◆ managedMemory

int hipDeviceProp_tR0000::managedMemory

Device supports allocating managed memory on this system.

◆ maxGridSize

int hipDeviceProp_tR0000::maxGridSize[3]

Max grid dimensions (XYZ).

◆ maxSharedMemoryPerMultiProcessor

size_t hipDeviceProp_tR0000::maxSharedMemoryPerMultiProcessor

Maximum Shared Memory Per Multiprocessor.

◆ maxTexture1D

int hipDeviceProp_tR0000::maxTexture1D

Maximum number of elements in 1D images.

◆ maxTexture1DLinear

int hipDeviceProp_tR0000::maxTexture1DLinear

Maximum size for 1D textures bound to linear memory.

◆ maxTexture2D

int hipDeviceProp_tR0000::maxTexture2D[2]

Maximum dimensions (width, height) of 2D images, in image elements.

◆ maxTexture3D

int hipDeviceProp_tR0000::maxTexture3D[3]

Maximum dimensions (width, height, depth) of 3D images, in image elements

◆ maxThreadsDim

int hipDeviceProp_tR0000::maxThreadsDim[3]

Max number of threads in each dimension (XYZ) of a block.

◆ maxThreadsPerBlock

int hipDeviceProp_tR0000::maxThreadsPerBlock

Max work items per work group or workgroup max size.

◆ maxThreadsPerMultiProcessor

int hipDeviceProp_tR0000::maxThreadsPerMultiProcessor

Maximum resident threads per multi-processor.

◆ memoryBusWidth

int hipDeviceProp_tR0000::memoryBusWidth

Global memory bus width in bits.

◆ memoryClockRate

int hipDeviceProp_tR0000::memoryClockRate

Max global memory clock frequency in khz.

◆ memPitch

size_t hipDeviceProp_tR0000::memPitch

Maximum pitch in bytes allowed by memory copies.

◆ minor

int hipDeviceProp_tR0000::minor

Minor compute capability. On HCC, this is an approximation and features may differ from CUDA CC. See the arch feature flags for portable ways to query feature caps.

◆ multiProcessorCount

int hipDeviceProp_tR0000::multiProcessorCount

Number of multi-processors (compute units).

◆ name

char hipDeviceProp_tR0000::name[256]

Device name.

◆ pageableMemoryAccess

int hipDeviceProp_tR0000::pageableMemoryAccess

Device supports coherently accessing pageable memory without calling hipHostRegister on it

◆ pageableMemoryAccessUsesHostPageTables

int hipDeviceProp_tR0000::pageableMemoryAccessUsesHostPageTables

Device accesses pageable memory via the host's page tables

◆ pciBusID

int hipDeviceProp_tR0000::pciBusID

PCI Bus ID.

◆ pciDeviceID

int hipDeviceProp_tR0000::pciDeviceID

PCI Device ID.

◆ pciDomainID

int hipDeviceProp_tR0000::pciDomainID

PCI Domain ID.

◆ regsPerBlock

int hipDeviceProp_tR0000::regsPerBlock

Registers per block.

◆ sharedMemPerBlock

size_t hipDeviceProp_tR0000::sharedMemPerBlock

Size of shared memory region (in bytes).

◆ tccDriver

int hipDeviceProp_tR0000::tccDriver

1:If device is Tesla device using TCC driver, else 0

◆ textureAlignment

size_t hipDeviceProp_tR0000::textureAlignment

Alignment requirement for textures.

◆ texturePitchAlignment

size_t hipDeviceProp_tR0000::texturePitchAlignment

Pitch alignment requirement for texture references bound to pitched memory

◆ totalConstMem

size_t hipDeviceProp_tR0000::totalConstMem