addr#
Size: 1 dword.
Operands: v
addr#
Size: 2 dwords.
Operands: v
data#
Instruction input.
Size: 1 dword.
Operands: v, a
data#
Instruction input.
Size: 2 dwords.
Operands: v, a
data#
Instruction input.
Size: 3 dwords.
Operands: v, a
data#
Instruction input.
Size: 4 dwords.
Operands: v, a
data0#
Instruction input.
Size: 1 dword.
Operands: v, a
data0#
Instruction input.
Size: 2 dwords.
Operands: v, a
data0#
Instruction input.
Size: 3 dwords.
Operands: v, a
data0#
Instruction input.
Size: 4 dwords.
Operands: v, a
data1#
Instruction input.
Size: 1 dword.
Operands: v, a
data1#
Instruction input.
Size: 2 dwords.
Operands: v, a
literal#
Size: 1 dword.
Operands: simm16
literal#
A floating-point_number, an integer_number, or an absolute_expression. The value is converted to f32 as described here.
literal#
An integer_number or an absolute_expression. The value is truncated to 32 bits.
saddr#
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
saddr#
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sbase#
A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
Size: 4 dwords.
Operands: s, ttmp
sbase#
A 64-bit base address for scalar memory operations.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sbase#
This operand is ignored by H/W and flat_scratch is supplied instead.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
scale_src0#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst
scale_src1#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst
sdata#
Input data for an atomic instruction.
Optionally may serve as an output data:
If glc is specified, gets the memory value before the operation.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sdata#
Input data for an atomic instruction.
Optionally may serve as an output data:
If glc is specified, gets the memory value before the operation.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sdata#
Input data for an atomic instruction.
Optionally may serve as an output data:
If glc is specified, gets the memory value before the operation.
Size: 4 dwords.
Operands: s, ttmp
sdata#
Instruction output.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sdata#
Instruction output.
Size: 1 dword.
Operands: simm8
sdata#
Instruction output.
Size: 16 dwords.
Operands: s, ttmp
sdata#
Instruction output.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sdata#
Instruction output.
Size: 4 dwords.
Operands: s, ttmp
sdata#
Instruction output.
Size: 8 dwords.
Operands: s, ttmp
sdst#
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec
sdst#
Instruction output.
Size: 1 dword if wavefront size is 32, otherwise 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sdst#
Instruction output.
Size: 1 dword if wavefront size is 32, otherwise 2 dwords.
Operands: vcc
sdst#
Instruction output.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sdst#
Instruction output.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec
sdst#
Instruction output.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
sdst#
Instruction output.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, exec
simm16#
Size: 1 dword.
Operands: simm16
simm16#
A 16-bit message code. The bits of this operand have the following meaning:
Bits
Description
Value Range
3:0
Message type.
0..15
6:4
Optional operation.
0..7
7:7
Unused.
-
9:8
Optional stream.
0..3
15:10
Unused.
-
This operand may be specified as one of the following:
An integer_number or an absolute_expression. The value must be in the range 0..0xFFFF.
A sendmsg value described below.
Sendmsg Value Syntax
Description
sendmsg(<type>)
A message identified by its type.
sendmsg(<type>,<op>)
A message identified by its type and operation.
sendmsg(<type>,<op>,<stream>)
A message identified by its type and operation with a stream id.
Type may be specified using message name or message id.
Op may be specified using operation name or operation id.
Stream id is an integer in the range 0..3.
Numeric values may be specified as positive integer numbers or absolute expressions.
Each message type supports specific operations:
Message name
Message Id
Supported Operations
Operation Id
Stream Id
MSG_INTERRUPT
1
-
-
-
MSG_GS
2
GS_OP_CUT
1
Optional
GS_OP_EMIT
2
Optional
GS_OP_EMIT_CUT
3
Optional
MSG_GS_DONE
3
GS_OP_NOP
0
-
GS_OP_CUT
1
Optional
GS_OP_EMIT
2
Optional
GS_OP_EMIT_CUT
3
Optional
MSG_SAVEWAVE
4
-
-
-
MSG_STALL_WAVE_GEN
5
-
-
-
MSG_HALT_WAVES
6
-
-
-
MSG_ORDERED_PS_DONE
7
-
-
-
MSG_EARLY_PRIM_DEALLOC
8
-
-
-
MSG_GS_ALLOC_REQ
9
-
-
-
MSG_GET_DOORBELL
10
-
-
-
MSG_SYSMSG
15
SYSMSG_OP_ECC_ERR_INTERRUPT
1
-
SYSMSG_OP_REG_RD
2
-
SYSMSG_OP_TTRACE_PC
4
-
Sendmsg arguments are validated depending on how type value is specified:
If message type is specified by name, arguments values must satisfy limitations detailed in the table above.
If message type is specified as a number, each argument must not exceed corresponding value range (see the first table).
Examples:
// numeric message code
msg = 0x10
s_sendmsg 0x12
s_sendmsg msg + 2
// sendmsg with strict arguments validation
s_sendmsg sendmsg(MSG_INTERRUPT)
s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
s_sendmsg sendmsg(MSG_GS, 2)
s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
s_sendmsg sendmsg(MSG_GET_DOORBELL)
// sendmsg with validation of value range only
msg = 2
op = 3
stream = 1
s_sendmsg sendmsg(msg, op, stream)
s_sendmsg sendmsg(2, GS_OP_CUT)
simm16#
A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
This operand may be specified as one of the following:
An integer_number or an absolute_expression. The value must be in the range -32768..32767.
A symbol (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
Examples:
offset = 30
label_1:
label_2 = . + 4
s_branch 32
s_branch offset + 2
s_branch label_1
s_branch label_2
s_branch label_3
s_branch label_4
label_3 = label_2 + 4
label_4:
simm16#
Bits of a hardware register being accessed.
The bits of this operand have the following meaning:
Bits
Description
Value Range
5:0
Register id.
0..63
10:6
First bit offset.
0..31
15:11
Size in bits.
1..32
This operand may be specified as one of the following:
An integer_number or an absolute_expression. The value must be in the range 0..0xFFFF.
An hwreg value described below.
Hwreg Value Syntax
Description
hwreg({0..63})
All bits of a register indicated by its id.
hwreg(<name>)
All bits of a register indicated by its name.
hwreg({0..63}, {0..31}, {1..32})
Register bits indicated by register id, first bit offset and size.
hwreg(<name>, {0..31}, {1..32})
Register bits indicated by register name, first bit offset and size.
Numeric values may be specified as positive integer numbers or absolute expressions.
Defined register names include:
Name
Description
HW_REG_MODE
Shader writeable mode bits.
HW_REG_STATUS
Shader read-only status.
HW_REG_TRAPSTS
Trap status.
HW_REG_HW_ID
Id of wave, simd, compute unit, etc.
HW_REG_GPR_ALLOC
Per-wave SGPR and VGPR allocation.
HW_REG_LDS_ALLOC
Per-wave LDS allocation.
HW_REG_IB_STS
Counters of outstanding instructions.
HW_REG_SH_MEM_BASES
Memory aperture.
HW_REG_TBA_LO
tba_lo register.
HW_REG_TBA_HI
tba_hi register.
HW_REG_TMA_LO
tma_lo register.
HW_REG_TMA_HI
tma_hi register.
Examples:
reg = 1
offset = 2
size = 4
hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
s_getreg_b32 s2, 0x1881
s_getreg_b32 s2, hwreg_enc // the same as above
s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
s_getreg_b32 s2, hwreg(15)
s_getreg_b32 s2, hwreg(51, 1, 31)
s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
simm16#
Counts of outstanding instructions to wait for.
The bits of this operand have the following meaning:
High Bits
Low Bits
Description
Value Range
15:14
3:0
VM_CNT: vector memory operations count.
0..63
-
6:4
EXP_CNT: export count.
0..7
-
11:8
LGKM_CNT: LDS, GDS, Constant and Message count.
0..15
This operand may be specified as one of the following:
An integer_number or an absolute_expression. The value must be in the range 0..0xFFFF.
A combination of vmcnt, expcnt, lgkmcnt and other values described below.
Syntax
Description
vmcnt(<N>)
A VM_CNT value. N must not exceed the largest VM_CNT value.
expcnt(<N>)
An EXP_CNT value. N must not exceed the largest EXP_CNT value.
lgkmcnt(<N>)
An LGKM_CNT value. N must not exceed the largest LGKM_CNT value.
vmcnt_sat(<N>)
A VM_CNT value computed as min(N, the largest VM_CNT value).
expcnt_sat(<N>)
An EXP_CNT value computed as min(N, the largest EXP_CNT value).
lgkmcnt_sat(<N>)
An LGKM_CNT value computed as min(N, the largest LGKM_CNT value).
These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
N is either an integer number or an absolute expression.
Examples:
vm_cnt = 1
exp_cnt = 2
lgkm_cnt = 3
cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8)
s_waitcnt cnt
s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above
s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above
s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above
s_waitcnt vmcnt(1)
s_waitcnt expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
soffset#
An offset added to the base address to get memory address.
If offset is specified as a register, it supplies an unsigned byte offset.
If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, m0
soffset#
An unsigned 20-bit offset added to the base address to get memory address.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, m0
soffset#
An unsigned byte offset.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst
src0#
Instruction input.
Size: 1 dword.
Operands: a
src0#
Instruction input.
Size: 1 dword.
Operands: v
src0#
Instruction input.
Size: 1 dword.
Operands: v, a
src0#
Instruction input.
Size: 1 dword.
Operands: v, lds_direct
src0#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst
src0#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst, literal
src0#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, lds_direct, fconst
src0#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, lds_direct, fconst, literal
src0#
Instruction input.
Size: 2 dwords.
Operands: v, a
src0#
Instruction input.
Size: 2 dwords.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst
src0#
Instruction input.
Size: 2 dwords.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst, literal
src0#
Instruction input.
Size: 4 dwords.
Operands: v, a
src0#
Instruction input.
Size: 8 dwords.
Operands: v, a
src0#
attr0.x through attr63.w, parameter attribute and channel to be interpolated
src1#
Instruction input.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, m0
src1#
Instruction input.
Size: 1 dword.
Operands: v, a
src1#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst
src1#
Instruction input.
Size: 16 dwords.
Operands: v
src1#
Instruction input.
Size: 2 dwords.
Operands: v, a
src1#
Instruction input.
Size: 2 dwords.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst
src1#
Instruction input.
Size: 4 dwords.
Operands: v, a
src1#
Instruction input.
Size: 8 dwords.
Operands: v, a
src2#
Instruction input.
Size: 1 dword.
Operands: v
src2#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst
src2#
Instruction input.
Size: 16 dwords.
Operands: v, a, fconst
src2#
Instruction input.
Size: 2 dwords.
Operands: v, a, fconst
src2#
Instruction input.
Size: 2 dwords.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst
src2#
Instruction input.
Size: 32 dwords.
Operands: v, a, fconst
src2#
Instruction input.
Size: 4 dwords.
Operands: v
src2#
Instruction input.
Size: 4 dwords.
Operands: v, a, fconst
src2#
Instruction input.
Size: 8 dwords.
Operands: v, a, fconst
srsrc#
Buffer resource constant which defines the address and characteristics of the buffer in memory.
Size: 4 dwords.
Operands: s, ttmp
ssrc0#
Instruction input.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
ssrc0#
Instruction input.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst, literal
ssrc0#
Instruction input.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp
ssrc0#
Instruction input.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst
ssrc0#
Instruction input.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst, literal
ssrc1#
Instruction input.
Size: 1 dword.
Operands:
ssrc1#
Instruction input.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst, literal
ssrc1#
Instruction input.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst
ssrc1#
Instruction input.
Size: 2 dwords.
Operands: s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst, literal
vaddr#
This is an optional operand which may specify offset and/or index.
Size: 0, 1 or 2 dwords. Size is controlled by modifiers offen and idxen:
If only idxen is specified, this operand supplies an index. Size is 1 dword.
If only offen is specified, this operand supplies an offset. Size is 1 dword.
If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
If none of these modifiers are specified, this operand must be set to off.
Operands: v
vcc#
Vector condition code.
Size: 1 dword.
Operands: vcc
vdata#
Input data for an atomic instruction.
Optionally may serve as an output data:
If glc is specified, gets the memory value before the operation.
Size: 1 dword.
Operands: v, a
vdata#
Input data for an atomic instruction.
Optionally may serve as an output data:
If glc is specified, gets the memory value before the operation.
Size: 2 dwords.
Operands: v, a
vdata#
Input data for an atomic instruction.
Optionally may serve as an output data:
If glc is specified, gets the memory value before the operation.
Size: 4 dwords.
Operands: v, a
vdata#
Instruction output.
Size: 1 dword.
Operands: v, a
vdata#
Instruction output.
Size: 2 dwords.
Operands: v, a
vdata#
Instruction output.
Size: 3 dwords.
Operands: v, a
vdata#
Instruction output.
Size: 4 dwords.
Operands: v, a
vdst#
Data returned by a 32-bit atomic flat instruction.
This is an optional operand. It must be used if and only if glc is specified.
Size: 1 dword.
Operands: v, a
vdst#
Data returned by a 64-bit atomic flat instruction.
This is an optional operand. It must be used if and only if glc is specified.
Size: 2 dwords.
Operands: v, a
vdst#
Instruction output.
Size: 1 dword.
Operands: a
vdst#
Instruction output.
Size: 1 dword.
Operands: s, flat_scratch, xnack_mask, ttmp
vdst#
Instruction output.
Size: 1 dword.
Operands: v
vdst#
Instruction output.
Size: 1 dword.
Operands: v, a
vdst#
Instruction output.
Size: 16 dwords.
Operands: v
vdst#
Instruction output.
Size: 16 dwords.
Operands: v, a
vdst#
Instruction output.
Size: 2 dwords.
Operands: v
vdst#
Instruction output.
Size: 2 dwords.
Operands: v, a
vdst#
Instruction output.
Size: 3 dwords.
Operands: v, a
vdst#
Instruction output.
Size: 32 dwords.
Operands: v
vdst#
Instruction output.
Size: 32 dwords.
Operands: v, a
vdst#
Instruction output.
Size: 4 dwords.
Operands: v
vdst#
Instruction output.
Size: 4 dwords.
Operands: v, a
vdst#
Instruction output.
Size: 6 dwords.
Operands: v
vdst#
Instruction output.
Size: 8 dwords.
Operands: v, a
vsrc0#
Instruction input.
Size: 1 dword.
Operands: a
vsrc0#
Instruction input.
Size: 1 dword.
Operands: v
vsrc0#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst
vsrc0#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst, literal
vsrc0#
Instruction input.
Size: 2 dwords.
Operands: v
vsrc0#
Instruction input.
Size: 2 dwords.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, exec, vccz, execz, scc, fconst
vsrc1#
Instruction input.
Size: 1 dword.
Operands: v
vsrc1#
Instruction input.
Size: 1 dword.
Operands: v, s, flat_scratch, xnack_mask, vcc, ttmp, m0, exec, vccz, execz, scc, fconst
vsrc1#
Instruction input.
Size: 2 dwords.
Operands: v