Data Structures#
Data Structures
Here are the data structures with brief descriptions:
[detail level 12]
| Camd_metrics_table_header_t | The following structures hold the gpu metrics values for a device |
| Camdsmi_asic_info_t | |
| ▼Camdsmi_bdf_t | |
| Cfields_ | |
| Camdsmi_board_info_t | |
| Camdsmi_clk_info_t | |
| Camdsmi_counter_value_t | |
| Camdsmi_ddr_bw_metrics_t | DDR bandwidth metrics |
| Camdsmi_dimm_power_t | DIMM Power(mW), power update rate(ms) and dimm address |
| Camdsmi_dimm_thermal_t | DIMM temperature(°C) and update rate(ms) and dimm address |
| Camdsmi_dpm_level_t | Max and min LCLK DPM level on a given NBIO ID. Valid max and min DPM level values are 0 - 1 |
| Camdsmi_dpm_policy_entry_t | The dpm policy |
| Camdsmi_dpm_policy_t | This structure holds information about dpm policies |
| Camdsmi_driver_info_t | |
| Camdsmi_engine_usage_t | |
| Camdsmi_error_count_t | This structure holds error counts |
| Camdsmi_evt_notification_data_t | |
| Camdsmi_freq_volt_region_t | This structure holds 2 amdsmi_range_t's, one for frequency and one for voltage. These 2 ranges indicate the range of possible values for the corresponding amdsmi_od_vddc_point_t |
| Camdsmi_frequencies_t | This structure holds information about clock frequencies |
| Camdsmi_frequency_range_t | |
| ▼Camdsmi_fw_info_t | |
| Cfw_info_list_ | |
| ▼Camdsmi_gpu_cache_info_t | |
| Ccache_ | |
| Camdsmi_gpu_metrics_t | |
| Camdsmi_link_id_bw_type_t | LINK name and Bandwidth type Information.It contains link names i.e valid link names are "P0", "P1", "P2", "P3", "P4", "G0", "G1", "G2", "G3", "G4" "G5", "G6", "G7" Valid bandwidth types 1(Aggregate_BW), 2 (Read BW), 4 (Write BW) |
| ▼Camdsmi_link_metrics_t | |
| C_links | |
| Camdsmi_name_value_t | This structure holds the name value pairs |
| Camdsmi_od_vddc_point_t | This structure represents a point on the frequency-voltage plane |
| Camdsmi_od_volt_curve_t | |
| Camdsmi_od_volt_freq_data_t | This structure holds the frequency-voltage values for a device |
| Camdsmi_pcie_bandwidth_t | This structure holds information about the possible PCIe bandwidths. Specifically, the possible transfer rates and their associated numbers of lanes are stored here |
| ▼Camdsmi_pcie_info_t | |
| Cpcie_metric_ | |
| Cpcie_static_ | |
| Camdsmi_power_cap_info_t | |
| Camdsmi_power_info_t | |
| Camdsmi_power_profile_status_t | This structure contains information about which power profiles are supported by the system for a given device, and which power profile is currently active |
| ▼Camdsmi_proc_info_t | |
| Cengine_usage_ | |
| Cmemory_usage_ | |
| Camdsmi_process_info_t | This structure contains information specific to a process |
| Camdsmi_range_t | This structure represents a range (e.g., frequencies or voltages) |
| Camdsmi_ras_feature_t | This structure holds ras feature |
| Camdsmi_retired_page_record_t | Reserved Memory Page Record |
| Camdsmi_smu_fw_version_t | This structure holds SMU Firmware version information |
| Camdsmi_temp_range_refresh_rate_t | Temperature range and refresh rate metrics of a DIMM |
| Camdsmi_utilization_counter_t | The utilization counter data |
| Camdsmi_vbios_info_t | |
| Camdsmi_version_t | This structure holds version information |
| Camdsmi_vram_info_t | |
| Camdsmi_vram_usage_t | |
| Camdsmi_xgmi_info_t |