.. meta::
  :description: Device software glossary for AMD GPUs
  :keywords: AMD, ROCm, GPU, device software, programming model, AMDGPU,
    assembly, IR, GFX IP, wavefront, work-group, HIP kernel, thread hierarchy

.. _glossary-device-software:

************************
Device software glossary
************************

This section provides brief definitions of software abstractions and programming
models that run on AMD GPUs.

.. glossary::
    :sorted:

    ROCm programming model
        The ROCm programming model defines how AMD GPUs execute massively
        parallel programs using hierarchical
        :term:`work-groups <Work-group (Block)>`, memory scopes, and barrier
        synchronization. See :ref:`hip:programming_model` for complete details.

    AMDGPU assembly
        AMDGPU assembly (GFX ISA) is the low-level assembly format for programs
        running on AMD GPUs, generated by the
        :term:`ROCm compiler toolchain <HIP compiler>`. See
        :ref:`hip:amdgpu_assembly` for instruction set details.

    AMDGPU intermediate representation
        AMDGPU IR is an intermediate representation for GPU code, serving as a
        virtual instruction set between high-level languages and
        :term:`architecture-specific assembly <AMDGPU assembly>`. See
        :ref:`hip:amdgpu_ir` for compilation details.

    LLVM target name
        The LLVM target name is a string identifier corresponding to a specific
        :term:`GFX IP <GFX IP>` version that is passed to the
        :term:`HIP compiler <HIP compiler>` toolchain to specify the target GPU
        architecture for code generation.
        See :doc:`llvm-project:reference/rocmcc` for details.

    Grid
        A grid represents the collection of all
        :term:`work-groups <Work-group (Block)>` executing a single
        :term:`kernel <HIP kernel>` across the entire GPU. See
        :ref:`hip:inherent_thread_hierarchy_grid` for grid execution details.

    HIP kernel
        A HIP kernel is the unit of GPU code that executes in parallel across
        many :term:`threads <Work-item (Thread)>`, distributed across the GPU's
        :term:`compute units <Compute units>`. See :ref:`hip:device_program` for
        kernel programming details.

    HIP thread hierarchy
        The thread hierarchy structures parallel work from individual
        :term:`threads <Work-item (Thread)>` to
        :term:`blocks <Work-group (Block)>` to :term:`grids <Grid>`, mapping
        onto hardware from :term:`SIMD lanes <SIMD core>` to
        :term:`compute units <Compute units>` to the entire GPU. See
        :ref:`hip:inherent_thread_model` for complete details.

    HIP memory hierarchy
        The memory hierarchy pairs each
        :term:`thread hierarchy <HIP thread hierarchy>` level with corresponding
        memory scopes, from :term:`private registers <Register>` to
        :term:`LDS <Local data share>` to :term:`GPU RAM <GPU RAM (VRAM)>`. See
        :ref:`hip:memory_hierarchy` for memory architecture details.

    Global memory
        Global memory is the :term:`device-wide memory <GPU RAM (VRAM)>`
        accessible to all :term:`threads <Work-item (Thread)>`, physically
        implemented as HBM or GDDR. See :ref:`hip:memory_hierarchy` for global
        memory details.